Multi-level bit-cell with non-linear polar material
An apparatus comprising a transistor having a gate terminal coupled to a word-line, wherein the transistor is further coupled to a bit-line. The apparatus further comprises a capacitor having a first terminal coupled to a plate-line and a second terminal coupled to the transistor, wherein the capacitor includes a non-linear polar material, and wherein the capacitor includes at least four stable states. In at least one example, the capacitor has a first polarization loop and a second polarization loop, wherein the second polarization loop is within the first polarization loop.
1 . An apparatus comprising:
a transistor having a gate terminal coupled to a word-line, wherein the transistor is further coupled to a bit-line; and
a capacitor having a first terminal coupled to a plate-line and a second terminal coupled to the transistor, wherein the capacitor includes a non-linear polar material, and wherein the capacitor includes at least four stable states, and wherein the capacitor includes:
a first capacitor with a first non-linear polar material; and
a second capacitor with a second non-linear polar material, wherein the first capacitor is coupled in parallel to the second capacitor.
2 . The apparatus of claim 1 , wherein the capacitor has a first polarization loop and a second polarization loop, and wherein the second polarization loop is within the first polarization loop.
3 . The apparatus of claim 2 , wherein first two states of the at least four stable states are part of the first polarization loop, and wherein second two states of the at least four stable states are part of the second polarization loop.
4 . The apparatus of claim 3 , wherein the at least four stable states include a first state, a second state, a third state, and a fourth state, and wherein a difference in voltages on the plate-line and the bit-line indicates a polarity, wherein the polarity is positive for the first state and the second state, and wherein the polarity is negative for the third state and the fourth state.
5 . The apparatus of claim 1 , further includes a circuitry to program the capacitor is by pulse width modulation or amplitude modulation of a voltage on the bit-line.
6 . The apparatus of claim 1 further includes a circuitry to write a first state to the capacitor prior to a second state to the capacitor, and wherein the first state is a different state than the second state, and wherein the second state is a target state.
7 . The apparatus of claim 1 , wherein the first non-linear polar material has a different thickness than the second non-linear polar material, and wherein first non-linear polar material has same doping as the second non-linear polar material.
8 . The apparatus of claim 1 , wherein the first non-linear polar material has a different doping than the second non-linear polar material, and wherein first non-linear polar material has a same thickness as the second non-linear polar material.
9 . The apparatus of claim 1 , wherein the capacitor further includes a resistive device coupled in series with the second capacitor, and wherein the resistive device and the second capacitor in combination are parallel to the first capacitor.
10 . The apparatus of claim 1 , wherein the first capacitor has a first polarization loop, and wherein the second capacitor has a second polarization loop which is different from the first polarization loop.
11 . The apparatus of claim 1 , wherein the non-linear polar material includes one of:
a form ABB′O 3 , wherein “A” includes one of: Ba, K, Bi, Y, La, Sc, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, T, Yb, Lu, Li, Bi, K, or Na, wherein “B” includes one of Mn, Fe, Ta, or Nb, and wherein “B′” includes one of: Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, or Zn;
a form AA′BO 3 , wherein “A” includes one of: Ba, K, Bi, Y, La, Sc, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, T, Yb, Lu, Li, Bi, K, or Na, wherein “B” includes one of Mn, Fe, Ta, or Nb, wherein “A′” includes one of Y, La, Sc, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, T, Yb, Lu, and wherein A′ comprises a valency of site A, but different ferroelectric polarizability from A;
a form ABO 3 , wherein “A” includes one of: Ba, K, Bi, Y, La, Sc, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, T, Yb, Lu, Li, Bi, K, or Na, and wherein “B” includes one of Mn, Fe, Ta, or Nb;
bismuth ferrite (BFO), BFO with a first doping material, wherein the first doping material is one of lanthanum, elements from lanthanide series of a periodic table, or elements of 3d, 4d, 5d, 6d, 4f, or 5 f series of periodic table;
lead zirconium titanate (PZT) or PZT with a second doping material, wherein the second doping material is one of La or Nb;
a perovskite material which includes one of: BaTiO 3 , PbTiO 3 , KNbO 3 , KNbO 3 , NaTaO 3 , wherein the perovskite material is doped with La or Lanthanides, chemically substituted lead titanate, and wherein Zr, La, or Nb is substituted in Ti site;
a relaxor ferroelectric material which includes one of: lead magnesium niobate (PMN), lead magnesium niobate-lead titanate (PMN-PT), lead lanthanum zirconate titanate (PLZT), lead scandium niobate (PSN), barium titanium-bismuth zinc niobium tantalum (BT-BZNT), or barium titanium-barium strontium titanium (BT-BST);
a BaTiO 3 (BTO) based relaxor which includes one of: BaTiO 3 —Bi(Zn 1/2 Ti 1/2 )O 3 (BTO-BZT), BaTiO 3 —BiScO 3 (BTO-BS): BiScO 3 , Ba (1-x) Sr x TiO 3 (BST), BaTiO 3 —Pb(Mg 1/3 Nb 2/3 )O 3 (BTO-PMN), BaTi (1-x) Zr x O 3 (BTZ), BaTiO 3 —Pb(Zn 1/3 Nb 2/3 )O 3 (BTO-PZN), BaTiO 3 —Pb(Sc 1/2 Nb 1/2 )O 3 (BTO-PSN);
a PZT based relaxor which includes one of: PZT-Pb(Mg 1/3 Nb 2/3 )O 3 (PZT-PMN), PZT-Pb(Ni 1/3 Nb 2/3 )O 3 (PZT-PNN), PZT-Pb(Zn 1/3 Nb 2/3 )O 3 (PZT-PZN), PZT-Pb(Sc 1/2 Nb 1/2 )O 3 (PZT-PSN), PZT-Pb(Fe 1/2 Nb 1/2 )O 3 (PZT-PFN), PZT-Pb(La, Zr, Ti)O 3 (PZT-PLZT), or PZT-Pb(Ti,Mn)O 3 (PZT-PTM);
a SrBi 2 Ta 2 O 9 (SBT) based relaxor which includes one of: paraelectric SBT-SrBi 2 (Nb,Ta) 2 O 9 (SBT-SBNT), or SBT doped with one of: Mn, Fe, Co, La, Ce or Nd, Ba, or Ca;
a first hexagonal ferroelectric which includes one of: YMnO 3 or LuFeO 3 ;
a second hexagonal ferroelectric of a type RMnO 3 , where R is a rare earth element which includes one of: cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr), promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium (Tm), ytterbium (Yb), or yttrium (Y);
lithium niobate, lithium tantalate, lithium iron tantalum oxy fluoride, barium strontium niobate, sodium barium niobate, or potassium strontium niobate;
an improper ferroelectric material which includes one of: [PTO/STO]n or [LAO/STO]n, wherein ‘n’ is between 1 and 100;
Hafnium (Hf), Zirconium (Zr), Aluminum (Al), Silicon (Si), their oxides or their alloyed oxides;
Hafnium oxides of a form Hf (1-x) E x O y , where E includes one of: Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, Zr, or Y, wherein ‘x’ and ‘y’ are first and second fractions, respectively;
HfO 2 doped with one of: Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, or Y;
Al (1-X) Sc (x) N, Ga (1-x) Sc (x) N, Al (1-X) Y (x) Nor Al (1-X-y) Mg (x) Nb (y) N, wherein ‘x’ and ‘y’ are third and fourth fractions, respectively; or
LiNbO 3 , LiTaO 3 , LiTaO 2 F 2 , Sr (x) Ba (1-x) Nb 2 O 6 where 0.32≤x≤0.8, or KSr 2 Nb 5 O 15 ; or
a paraelectric material comprising SrTiO 3 , Ba (x) Sr (y) TiO 3 , HfZrO 2 , Hf—Si—O, or La-substituted PbTiO 3 .
12 . A system comprising:
a processor;
a memory coupled to the processor; and
a communication circuitry coupled to the processor, wherein the memory includes a bit-cell that includes:
a transistor having a gate terminal coupled to a word-line, wherein the transistor is further coupled to a bit-line; and
a capacitor having a first terminal coupled to a plate-line and a second terminal coupled to the transistor, wherein the capacitor includes a non-linear polar material, wherein the capacitor includes at least four stable states,
and wherein the capacitor includes:
a first capacitor with a first non-linear polar material; and
a second capacitor with a second non-linear polar material, wherein the first capacitor is coupled in parallel to the second capacitor.
13 . The system of claim 12 , wherein the capacitor has a first polarization loop and a second polarization loop, and wherein the second polarization loop is within the first polarization loop.
14 . The system of claim 13 , wherein first two states of the at least four stable states are part of the first polarization loop, and wherein second two states of the at least four stable states are part of the second polarization loop.
15 . The system of claim 12 , wherein the memory includes a circuitry to program the capacitor by pulse width modulation or amplitude modulation of a voltage on the bit-line.
16 . The system of claim 12 , wherein the memory includes a circuitry to write a first state to the capacitor prior to a second state to the capacitor, wherein the first state is a different state than the second state, and wherein the second state is a target state.
17 . A method comprising:
forming a transistor having a gate terminal coupled to a word-line, wherein the transistor is further coupled to a bit-line; and
forming a capacitor having a first terminal coupled to a plate-line and a second terminal coupled to the transistor, wherein the capacitor includes a non-linear polar material, and wherein the capacitor includes at least four stable states, and wherein the capacitor includes:
a first capacitor with a first non-linear polar material; and
a second capacitor with a second non-linear polar material, wherein the first capacitor is coupled in parallel to the second capacitor.
18 . The method of claim 17 , wherein the capacitor has a first polarization loop and a second polarization loop, and wherein the second polarization loop is within the first polarization loop.
19 . The method of claim 18 , wherein first two states of the at least four stable states are part of the first polarization loop, and wherein second two states of the at least four stable states are part of the second polarization loop.