Streaming mode for accessing memory cells in a memory device
Systems, methods, and apparatus for a memory device. In one approach, a memory device selectively enters a streaming mode when accessing memory cells in a memory array. A controller determines for new read operations whether memory cells will be accessed in a streaming mode or in a random mode. First memory cells addressed using a wordline are read by the controller. The wordline is charged to an initial voltage for reading the first memory cells. When in the streaming mode, instead of discharging the wordline after reading the first memory cells, as is done for a random mode, the controller keeps a minimum bias on the wordline and returns the wordline again to the initial voltage for performing a next read operation to read second memory cells. This saves memory device power.
1 . An apparatus comprising:
sensing circuitry configured to read memory cells; and
a controller configured to:
bias a voltage of a wordline to an initial voltage;
read, with the sensing circuitry, first memory cells;
after the first memory cells are read, bias the wordline to return the voltage of the wordline to the initial voltage; and
read, with the sensing circuitry after the wordline is returned to the initial voltage, second memory cells, wherein the wordline is not discharged to zero volts between the first memory cells being read and the second memory cells being read.
2 . The apparatus of claim 1 , wherein:
prior to reading the first memory cells, the voltage of the wordline is biased to the initial voltage from a voltage corresponding to an idle mode; and
after reading the second memory cells, the voltage of the wordline is biased to the voltage corresponding to the idle mode.
3 . The apparatus of claim 1 , wherein the controller is further configured to:
determine that the first and second memory cells are accessed using a same wordline;
wherein the wordline is biased to return the voltage of the wordline to the initial voltage in response to determining that the first and second memory cells are accessed using the same wordline.
4 . The apparatus of claim 3 , wherein the determination is performed after reading the first memory cells.
5 . The apparatus of claim 1 , wherein the controller is further configured to:
determine, after reading each of the first and second memory cells, whether to return the voltage of the wordline to the initial voltage in preparation for performing a next read operation, or to a voltage corresponding to an idle mode in which the wordline is unselected.
6 . The apparatus of claim 5 , wherein the next read operation is performed after reading the second memory cells, and the next read operation comprises reading third memory cells that are accessed using the wordline.
7 . The apparatus of claim 5 , wherein the controller is further configured to:
after reading the second memory cells, determine an address of data corresponding to a new read command received from a host device; and
based on the address of the data corresponding to the new read command, return the voltage of the wordline to the voltage corresponding to the idle mode.
8 . The apparatus of claim 1 , wherein the controller is further configured to bias first digit lines used to access the first memory cells.
9 . The apparatus of claim 8 , wherein the first digit lines are biased in preparation for reading the first memory cells.
10 . The apparatus of claim 9 , wherein the controller is further configured to bias second digit lines used to access the second memory cells.
11 . The apparatus of claim 10 , wherein after reading the first memory cells, the first digit lines are unselected, and the second digit lines are selected in preparation for reading the second memory cells.
12 . The apparatus of claim 8 , wherein the first digit lines are biased after the voltage of the wordline is at the initial voltage.
13 . The apparatus of claim 1 , wherein reading each of the first and second memory cells includes ramping the voltage of the wordline.
14 . The apparatus of claim 13 , wherein the voltage of the wordline is ramped until a condition is satisfied.
15 . The apparatus of claim 14 , wherein the condition is based on determining that at least one memory cell has switched.
16 . The apparatus of claim 1 , wherein the controller is further configured to:
bias a gate line to electrically connect bias circuitry to first digit lines used to access the first memory cells; and
after biasing the gate line, bias the first digit lines to a voltage sufficient for reading the first memory cells.
17 . The apparatus of claim 1 , wherein the controller is further configured to:
bias at least one sensing node to a first voltage sufficient for sensing the first memory cells;
wherein the sensing node is electrically coupled to the sensing circuitry and to the first memory cells, and wherein the sensing node discharges to a second voltage in response to at least one of the first memory cells switching.
18 . The apparatus of claim 1 , wherein the controller is further configured to:
after reading the first memory cells, bias a sensing node in preparation for reading the second memory cells.
19 . The apparatus of claim 1 , wherein the wordline used to read the first memory cells and the wordline used to read the second memory cells is a single, common wordline.
20 . The apparatus of claim 1 , wherein the wordline is not discharged to an idle mode voltage between the first memory cells being read and the second memory cells being read.
21 . The apparatus of claim 1 , wherein the initial voltage is a non-zero voltage level.
22 . The apparatus of claim 1 , wherein the first memory cells are read at a different voltage from the initial voltage.
23 . The apparatus of claim 1 , wherein the second memory cells are read at a different voltage from the initial voltage.
24 . The apparatus of claim 1 , wherein the first memory cells are read at a first voltage different from the initial voltage, the second memory cells are read at a second voltage different from the initial voltage, and the first voltage is different from the second voltage.
25 . An apparatus comprising:
sensing circuitry configured to read first and second memory cells sequentially;
and a controller configured to:
read, with the sensing circuitry, the first memory cells, including increasing a magnitude of a voltage of a wordline from an initial voltage; and
read, with the sensing circuitry, the second memory cells, including increasing a magnitude of the voltage of the wordline from the initial voltage,
wherein the wordline is returned to the initial voltage between the first memory cells being read and the second memory cells being read, and
wherein the wordline is not discharged to zero volts between the first memory cells being read and the second memory cells being read.
26 . The apparatus of claim 25 , wherein the controller is further configured to:
receive a command to read data stored in the first and second memory cells, wherein the first and second memory cells are accessed using the wordline; and
in response to receiving the command, bias a voltage of the wordline to the initial voltage.
27 . A method comprising:
reading, by a controller using a sensing circuitry of a memory device, first memory cells of the memory device, wherein the reading of the first memory cells includes increasing a magnitude of a voltage of a wordline from an initial voltage; and
reading, by the controller using the sensing circuitry, second memory cells of the memory device, wherein the reading of the second memory cells includes increasing a magnitude of the voltage of the wordline from the initial voltage,
wherein the wordline is returned to the initial voltage between the first memory cells being read and the second memory cells being read.
28 . The method of claim 27 , wherein the wordline is not discharged to zero volts between the first memory cells being read and the second memory cells being read.
29 . The method of claim 27 , wherein the first memory cells are read at a first voltage different from the initial voltage, the second memory cells are read at a second voltage different from the initial voltage, and the first voltage is different from the second voltage.
30 . An apparatus comprising:
sensing circuitry configured to read memory cells; and
a controller configured to:
bias a voltage of a wordline to an initial voltage;
read, with the sensing circuitry, first memory cells, wherein the first memory cells are read at a first voltage different from the initial voltage;
after the first memory cells are read, bias the wordline to return the voltage of the wordline to the initial voltage; and
read, with the sensing circuitry after the wordline is returned to the initial voltage, second memory cells, wherein the second memory cells are read at a second voltage different from the initial voltage, and wherein the first voltage is different from the second voltage.