Vertical memory device with a double word line structure
A memory device includes: a substrate; a bit line which is vertically oriented from the substrate; a plate line which is vertically oriented from the substrate; and a memory cell provided with a transistor and a capacitor that are positioned in a lateral arrangement between the bit line and the plate line, wherein the transistor includes: an active layer which is laterally oriented to be parallel to the substrate between the bit line and the capacitor; and a line-shaped lower word line and a line-shaped upper word line vertically stacked with the active layer therebetween and oriented to intersect with the active layer.
1 . A memory device, comprising:
a memory cell array including a plurality of memory cells,
wherein each of the memory cells comprises:
a capacitor comprising a lateral cylindrical shaped structure;
an active layer coupled to the capacitor; and
a pair of word lines comprising a lower word line disposed under the active layer and an upper word line disposed over the active layer.
2 . The memory device of claim 1 , wherein the memory cell comprising at least one gate dielectric layer individually disposed between upper and lower surfaces of the active layer and the lower and the upper word lines.
3 . The memory device of claim 2 , wherein the at least one gate dielectric layer surrounds the active layer.
4 . The memory device of claim 2 , wherein the at least one gate dielectric layer is disposed on top of the upper and lower surfaces of the active layer.
5 . The memory device of claim 2 , wherein the lower word line and the upper word line is disposed on top of the at least one gate dielectric layer.
6 . The memory device of claim 1 , wherein the lower word line and the upper word line have a line-shaped structure.
7 . The memory device of claim 1 , wherein the upper word line and the lower word line are electrically connected to each other.
8 . The memory device of claim 1 , wherein the memory cell array comprises a bit line electrically connected to the active layer, the bit line vertically oriented from a substrate.
9 . The memory device of claim 1 , further comprising:
a peripheral circuit portion for controlling the memory cell array.
10 . The memory device of claim 9 , further comprising:
a plurality of bonding pads,
wherein the memory cell array and the peripheral circuit portion are electrically connected to each other through the bonding pads.
11 . The memory device of claim 1 , wherein the capacitor includes:
a first node coupled to the active layer;
a second node over the first node; and
a dielectric material between the first node and the second node.
12 . The memory device of claim 11 , wherein the first node of the capacitor has a lateral cylindrical shape.
13 . The memory device of claim 12 , wherein the second node of the capacitor includes:
an inner second node extending into the cylindrical shape of the first node; and
a plurality of outer second nodes surrounding an outside of the cylindrical shape of the first node.