IP Library › Granted Patent US 12712017
Granted Patent B1
US 12712017 · App. 18/790,335 · Granted Aug 18, 2026

Static random access memory cell

Inventors: Rouwaida Nawaf Kanj (Cedar Park, TX); John Edward Barth (Hobe Sound, FL)
Assignee: Synopsys, Inc.
G11C11/419G11C11/418
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Quick Facts
Patent No.
US 12712017
App. No.
18/790,335
Granted
Aug 18, 2026
Kind
B1
Abstract

An SRAM cell includes four PMOS and four NMOS transistors. The first PMOS and NMOS form a first inverter. The second PMOS and NMOS form a second inverter having an output coupled to an input (first node) of the first inverter, and an input coupled to an output (second node) of the first inverter. The third NMOS has its source coupled to the second node, drain coupled to a first bitline, and gate coupled to a third node. The fourth NMOS has its source coupled to the first node, drain coupled to a second bitline, and gate coupled to a fourth node. The third PMOS has its drain coupled to the first node, source coupled to the second bitline, and gate coupled to a fifth node. The fourth PMOS has its drain coupled to the second node, source coupled to the first bitline, and gate coupled to a sixth node.

Claims (52)

1 . A static random access memory (SRAM) cell comprising:

a first PMOS transistor having a source terminal coupled to a supply voltage and a gate terminal coupled to a first node;

a first NMOS transistor having a source terminal receiving a ground voltage, a gate terminal coupled to the first node, and a drain terminal coupled to the drain terminal of the first PMOS transistor;

a second PMOS transistor having a source terminal coupled to the supply voltage and a gate terminal coupled to a second node;

a second NMOS transistor having a source terminal receiving the ground voltage, a gate terminal coupled to the second node, and a drain terminal coupled to the drain terminal of the second PMOS transistor and the first node, wherein the drain terminals of the first PMOS and first NMOS transistors are coupled to the second node;

a third NMOS transistor having a source/drain terminal coupled to the second node, a drain/source terminal coupled to a first bitline, and a gate terminal coupled to a third node;

a fourth NMOS transistor having a source/drain terminal coupled to the first node, a drain/source terminal coupled to a second bitline, and a gate terminal coupled to a fourth node;

a third PMOS transistor having a drain/source terminal coupled to the first node, a source/drain terminal coupled to the second bitline, and a gate terminal coupled to a fifth node; and

a fourth PMOS transistor having a drain/source terminal coupled to the second node, a source/drain terminal coupled to the first bitline, and a gate terminal coupled to a sixth node, wherein the third node, the fourth node, the fifth node and the sixth node are different nodes.

2 . The SRAM cell of claim 1 , wherein to perform a write operation, during a first time period, the third PMOS transistor and the third NMOS transistor are turned on, and the fourth PMOS transistor and the fourth NMOS transistor are turned off.

3 . The SRAM cell of claim 2 , wherein to perform the write operation, during a second time period, the fourth PMOS transistor and the fourth NMOS transistor are turned on, and the third PMOS transistors and the third NMOS transistor are turned off.

4 . The SRAM cell of claim 3 , wherein to perform a read operation, during a third time period, the third PMOS transistor and the third NMOS transistor are turned on, and the fourth PMOS transistor and the fourth NMOS transistor are turned off.

5 . The SRAM cell of claim 4 , wherein to perform the read operation, during a fourth time period, the fourth PMOS transistor and the fourth NMOS transistor are turned on, and the third PMOS transistor and the third NMOS transistor are turned off.

6 . The SRAM cell of claim 3 , wherein to perform a read operation, during a third time period, the third NMOS transistor and the fourth NMOS transistor are turned on.

7 . The SRAM cell of claim 1 further comprising:

a fifth NMOS transistor having a gate terminal coupled to the first node, and a source terminal receiving the ground voltage; and

a sixth NMOS transistor having a gate terminal coupled to a seventh node, a source terminal coupled to a drain terminal of the fifth NMOS transistor, and a drain terminal coupled to a third bitline.

8 . The SRAM cell of claim 7 , wherein during a write operation the first bitline is coupled to the second node and the second bitline is coupled to the first node, and during a read operation the first node is coupled to the third bitline.

9 . A system comprising:

a memory storing instructions; and

a processor, coupled with the memory and configured to execute the instructions, the instructions when executed causing the processor to:

generate data representative of a first PMOS transistor having a source terminal coupled to a supply voltage and a gate terminal coupled to a first node;

generate data representative of a first NMOS transistor having a source terminal receiving a ground voltage, a gate terminal coupled to the first node, and a drain terminal coupled to the drain terminal of the first PMOS transistor;

generate data representative of a second PMOS transistor having a source terminal coupled to the supply voltage and a gate terminal coupled to a second node;

generate data representative of a second NMOS transistor having a source terminal receiving the ground voltage, a gate terminal coupled to the second node, and a drain terminal coupled to the drain terminal of the second PMOS transistor and the first node, wherein the drain terminals of the first PMOS and first NMOS transistors are coupled to the second node;

generate data representative of a third NMOS transistor having a source/drain terminal coupled to the second node, a drain/source terminal coupled to a first bitline, and a gate terminal coupled to a third node;

generate data representative of a fourth NMOS transistor having a source/drain terminal coupled to the first node, a drain/source terminal coupled to a second bitline, and a gate terminal coupled to a fourth node;

generate data representative of a third PMOS transistor having a drain/source terminal coupled to the first node, a source/drain terminal coupled to the second bitline, and a gate terminal coupled to a fifth node; and

generate data representative of a fourth PMOS transistor having a drain/source terminal coupled to the second node, a source/drain terminal coupled to the first bitline, and a gate terminal coupled to a sixth node, wherein the third node, the fourth node, the fifth node and the sixth node are different nodes.

10 . The system of claim 9 , wherein to perform a write operation, during a first time period, the third PMOS transistor and the third NMOS transistor are turned on, and the fourth PMOS transistor and the fourth NMOS transistor are turned off.

11 . The system of claim 10 , wherein to perform the write operation, during a second time period, the fourth PMOS transistor and the fourth NMOS transistor are turned on, and the third PMOS transistor and the third NMOS transistor are turned off.

12 . The system of claim 11 , wherein to perform a read operation, during a third time period, the third PMOS transistor and the third NMOS transistor are turned on, and the fourth PMOS transistor and the fourth NMOS transistor are turned off.

13 . The system of claim 12 , wherein to perform the read operation, during a fourth time period, the fourth PMOS transistor and the fourth NMOS transistor are turned on, and the third PMOS transistor and the third NMOS transistor are turned off.

14 . The system of claim 9 , wherein the instructions further cause the processor to:

generate data representative of a fifth NMOS transistor having a gate terminal coupled to the first node, and a source terminal receiving the ground voltage; and

generate data representative of a sixth NMOS transistor having a gate terminal coupled to a seventh node, a source terminal coupled to a drain terminal of the fifth NMOS transistor, and a drain terminal coupled to a third bitline.

15 . A non-transitory computer readable medium comprising stored instructions, which when executed by a processor, cause the processor to:

generate data representative of a first PMOS transistor having a source terminal coupled to a supply voltage and a gate terminal coupled to a first node;

generate data representative of a first NMOS transistor having a source terminal receiving a ground voltage, a gate terminal coupled to the first node, and a drain terminal coupled to the drain terminal of the first PMOS transistor;

generate data representative of a second PMOS transistor having a source terminal coupled to the supply voltage and a gate terminal coupled to a second node;

generate data representative of a second NMOS transistor having a source terminal receiving the ground voltage, a gate terminal coupled to the second node, and a drain terminal coupled to the drain terminal of the second PMOS transistor and the first node, wherein the drain terminals of the first PMOS and first NMOS transistors are coupled to the second node;

generate data representative of a third NMOS transistor having a source/drain terminal coupled to the second node, a drain/source terminal coupled to a first bitline, and a gate terminal coupled to a third node;

generate data representative of a fourth NMOS transistor having a source/drain terminal coupled to the first node, a drain/source terminal coupled to a second bitline, and a gate terminal coupled to a fourth node;

generate data representative of a third PMOS transistor having a drain/source terminal coupled to the first node, a source/drain terminal coupled to the second bitline, and a gate terminal coupled to a fifth node; and

generate data representative of a fourth PMOS transistor having a drain/source terminal coupled to the second node, a source/drain terminal coupled to the first bitline, and a gate terminal coupled to a sixth node, wherein the third node, the fourth node, the fifth node and the sixth node are different nodes.

16 . The non-transitory computer readable medium of claim 15 , wherein to perform a write operation, during a first time period, the third PMOS transistor and the third NMOS transistor are turned on, and the fourth PMOS transistor and the fourth NMOS transistor are turned off.

17 . The non-transitory computer readable medium of claim 16 , wherein to perform the write operation, during a second time period, the fourth PMOS transistor and the fourth NMOS transistor are turned on, and the third PMOS transistor and the third NMOS transistors are turned off.

18 . The non-transitory computer readable medium of claim 17 , wherein to perform a read operation, during a third time period, the third PMOS transistor and the third NMOS transistor are turned on, and the fourth PMOS transistor and the fourth NMOS transistor are turned off.

19 . The non-transitory computer readable medium of claim 18 , wherein to perform the read operation, during a fourth time period, the fourth PMOS transistor and the fourth NMOS transistor are turned on, and the third PMOS transistor and the third NMOS transistor are turned off.

20 . The non-transitory computer readable medium of claim 19 , wherein the instructions further cause the processor to:

generate data representative of a fifth NMOS transistor having a gate terminal coupled to the first node, and a source terminal receiving the ground voltage; and

generate data representative of a sixth NMOS transistor having a gate terminal coupled to a seventh node, a source terminal coupled to a drain terminal of the sixth NMOS transistor, and a drain terminal coupled to a third bitline.