Segmented reference for tracking column loading
A semiconductor device including at least one sense amplifier, a first memory array that includes first segments of first memory cells situated on a first side of the at least one sense amplifier, a second memory array that includes second segments of second memory cells situated on a second side of the at least one sense amplifier, first reference cells connected to first reference word lines in the first memory array for sensing data from the second memory cells and second reference cells connected to second reference word lines in the second memory array for sensing data from the first memory cells. The first reference cells connected to one of the first reference word lines for sensing data from one of the second segments and the first reference cells connected to another one of the first reference word lines for sensing data from another one of the second segments.
1 . A semiconductor device, comprising:
at least one sense amplifier;
a first memory array that includes first segments of first memory cells situated on a first side of the at least one sense amplifier;
a second memory array that includes second segments of second memory cells situated on a second side of the at least one sense amplifier that is different than the first side of the at least one sense amplifier;
first reference cells connected to first reference word lines in the first memory array and configured to provide first reference signals for sensing data from the second memory cells in the second memory array; and
second reference cells connected to second reference word lines in the second memory array and configured to provide second reference signals for sensing data from the first memory cells in the first memory array,
wherein the first reference cells connected to one of the first reference word lines are configured to provide the first reference signals for sensing data from one of the second segments and the first reference cells connected to another one of the first reference word lines are configured to provide the first reference signals for sensing data from another one of the second segments, and
wherein the second reference cells connected to one of the second reference word lines are configured to provide the second reference signals for sensing data from one of the first segments and the second reference cells connected to another one of the second reference word lines are configured to provide the second reference signals for sensing data from another one of the first segments.
2 . The device of claim 1 , wherein at least one of the first segments has a segment word line size of sixteen to sixty-four word lines.
3 . The device of claim 1 , wherein at least one of the first segments that is close to an edge of the first memory array has a segment word line size of four to eight word lines.
4 . The device of claim 1 , wherein an area overhead for reference word lines and trim code is one to five percent of the device.
5 . The device of claim 1 , wherein each of the first reference word lines is in the middle of a corresponding one of the first segments.
6 . The device of claim 1 , wherein each first segment of the first segments includes multiple first reference word lines.
7 . The device of claim 6 , wherein one of the multiple first reference word lines is for sensing data from an even word line and another one of the multiple first reference word lines is for sensing data from an odd word line.
8 . The device of claim 6 , wherein the multiple first reference word lines are situated in the middle of the first segment.
9 . The device of claim 6 , wherein an even first reference word line is situated on one edge of the first segment and an odd first reference word line is situated on an opposite edge of the first segment.
10 . The device of claim 1 , wherein a first word line size of the first segments is based on column loading effects including bit line/source line resistance variations of the first memory cells.
11 . The method of claim 10 , wherein denser second reference word lines improve tracking of the bit line/source line resistance variations of the first memory cells.
12 . A semiconductor device, comprising:
at least one sense amplifier;
a first memory array that includes first segments of first memory cells situated on a first side of the at least one sense amplifier;
a second memory array that includes second segments of second memory cells situated on a second side of the at least one sense amplifier;
first reference word lines connected to first reference cells in the first memory array for sensing data from the second memory cells in the second memory array; and
second reference word lines connected to second reference cells in the second memory array for sensing data from the first memory cells in the first memory array,
wherein at least one of the second segments includes sixteen to sixty-four word lines and each of the first reference word lines is configured for sensing data from a different one of the second segments and at least one of the first segments includes sixteen to sixty-four word lines and each of the second reference word lines is configured for sensing data from a different one of the first segments.
13 . The device of claim 12 , wherein a first word line size of the first segments is based on column loading effects including bit line/source line resistance variations of the first memory cells and denser second reference word lines improve tracking of the bit line/source line resistance variations of the first memory cells.
14 . The device of claim 12 , wherein at least one of the first segments that is close to an edge of the first memory array has a segment word line size of four to eight word lines.
15 . The device of claim 12 , wherein each of the first reference word lines is in the middle of a corresponding one of the first segments.
16 . The device of claim 12 , wherein each first segment of the first segments includes multiple first reference word lines and one of the multiple first reference word lines is for sensing data from an even word line and another one of the multiple first reference word lines is for sensing data from an odd word line.
17 . The device of claim 12 , wherein each first segment of the first segments includes multiple first reference word lines situated in the middle of the first segment.
18 . A method of operating a semiconductor device, the method comprising:
selecting a first memory cell from one segment of multiple first segments in a first memory array that is situated on one side of at least one sense amplifier;
selecting a first reference cell from one segment of multiple second segments in a second memory array that is situated on another side of the at least one sense amplifier;
comparing data from the first memory cell to reference signals from the first reference cell to determine a first stored data value;
selecting a second memory cell from the one segment of the multiple second segments in the second memory array;
selecting a second reference cell from the one segment of the multiple first segments in the first memory array; and
comparing data from the second memory cell to reference signals from the second reference cell to determine a second stored data value.
19 . The method of claim 18 , wherein selecting the first reference cell includes selecting a first reference word line from the middle of the one segment of the multiple second segments.
20 . The method of claim 18 , wherein selecting the first reference cell includes selecting from the one segment of the multiple second segments one of multiple first reference word lines for sensing data from an even word line or selecting from the one segment of the multiple second segments another one of the multiple first reference word lines for sensing data from an odd word line.