Recursive analog content addressable memory device
A recursive Analog Content Addressable Memory (ACAM) device includes a first comparison stage and a second comparison stage. The first comparison stage includes a first match line, a first base segment comparator connected between the first match line and a reference node, a first incremented segment comparator, and a first pass transistor. The first pass transistor and the first incremented segment comparator are connected in series between the first match line and the reference node. The second comparison stage includes a first inverter connected to the first pass transistor, a second match line connected to the first inverter, and a second base segment comparator connected between the second match line and the reference node. The device enables efficient comparison of multi-bit values.
1 . A device comprising:
a first comparison stage comprising:
a first match line;
a first base segment comparator connected between the first match line and a reference node;
a first incremented segment comparator; and
a first pass transistor, the first pass transistor and the first incremented segment comparator being connected in series between the first match line and the reference node; and
a second comparison stage comprising:
a first inverter connected to the first pass transistor;
a second match line connected to the first inverter; and
a second base segment comparator connected between the second match line and the reference node.
2 . The device of claim 1 , wherein the second comparison stage further comprises:
a second incremented segment comparator; and
a second pass transistor, the second pass transistor and the second incremented segment comparator being connected in series between the second match line and the reference node.
3 . The device of claim 1 , wherein the second comparison stage further comprises:
a second incremented segment comparator; and
a least significant segment comparator, the least significant segment comparator and the second incremented segment comparator being connected in series between the second match line and the reference node.
4 . The device of claim 1 , wherein the first base segment comparator, the first incremented segment comparator, and the second base segment comparator are analog content addressable memory cells.
5 . The device of claim 4 , wherein each of the analog content addressable memory cells are configured to compare an input value to a stored threshold and output a match signal when the input value is greater than or equal to the stored threshold.
6 . The device of claim 1 , further comprising:
a third comparison stage comprising:
a third match line;
a third incremented segment comparator connected between the third match line and the reference node;
a third base segment comparator; and
a second pass transistor, the second pass transistor and the third base segment comparator being connected in series between the third match line and the reference node; and
a fourth comparison stage comprising:
a second inverter connected to the second pass transistor;
a fourth match line connected to the second inverter; and
a fourth incremented segment comparator connected between the fourth match line and the reference node.
7 . The device of claim 6 , further comprising:
a first sense amplifier connected to the first match line;
a second sense amplifier connected to the third match line; and
an AND gate connected to the first sense amplifier and the second sense amplifier.
8 . The device of claim 6 , further comprising:
a third pass transistor connected between the fourth match line and the reference node; and
a third inverter connected to the third pass transistor, the first match line connected to the third inverter.
9 . A device comprising:
a lower bound comparison circuit comprising first comparison stages, each of the first comparison stages comprising a first match line and a first analog content addressable memory connected between the first match line and a reference node, wherein the first match lines of adjacent one of the first comparison stages are serially connected;
an upper bound comparison circuit comprising second comparison stages, each of the second comparison stages comprising a second match line and a second analog content addressable memory connected between the second match line and the reference node, wherein the second match lines of adjacent one of the second comparison stages are serially connected; and
a combining circuit connected to the lower bound comparison circuit and the upper bound comparison circuit.
10 . The device of claim 9 , wherein the lower bound comparison circuit and the upper bound comparison circuit comprise recursive comparators.
11 . The device of claim 9 , wherein the combining circuit is configured to combine outputs from the lower bound comparison circuit and the upper bound comparison circuit in the digital domain.
12 . The device of claim 9 , wherein the combining circuit is configured to combine outputs from the lower bound comparison circuit and the upper bound comparison circuit in the analog domain.
13 . The device of claim 9 , wherein each of the first and second analog content addressable memories comprises a memristor configured to store a same predetermined number of bits.
14 . The device of claim 9 , wherein each of the first and second analog content addressable memories comprises a memristor, a first subset of the memristors are configured to store a first number of bits, and a second subset of the memristors are configured to store a second number of bits, the second number different from the first number.
15 . The device of claim 9 , wherein each of the first and second analog content addressable memories comprises a memristor configured to store a number of bits, the number of bits being in a range of three to four.
16 . A method comprising:
partitioning a range into a plurality of bit segments, the range having a higher precision than the bit segments;
storing the bit segments in comparison stages, each of the comparison stages comprising a match line and an analog content addressable memory connected between the match line and a reference node, wherein the match lines of adjacent one of the comparison stages are serially connected;
partitioning an input value into a plurality of analog inputs; and
comparing the analog inputs against the bit segments to determine whether the input value falls in the range.
17 . The method of claim 16 , wherein the bit segments have equal bit length.
18 . The method of claim 16 , wherein the bit segments have unequal bit length.
19 . The method of claim 16 , wherein the range comprises a lower bound and an upper bound, wherein the comparison stages comprise first comparison stages for the lower bound and second comparison stages for the upper bound, and the method further comprises:
combining results from the first comparison stages and the second comparison stages using a logical AND operation.
20 . The method of claim 16 , wherein the range comprises a lower bound and an upper bound, wherein the comparison stages comprise first comparison stages for the lower bound and second comparison stages for the upper bound, and the method further comprises:
combining results from the first comparison stages and the second comparison stages using an inverter and a pass transistor.