IP Library › Granted Patent US 12712024
Granted Patent B2
US 12712024 · App. 18/935,014 · Granted Aug 18, 2026

Memory, memory programming method and memory system

Inventors: Man Hu (Wuhan, CN); HongTao Liu (Wuhan, CN); XiangNan Zhao (Wuhan, CN)
Assignee: Yangtze Memory Technologies Co., Ltd.
G11C16/102G11C16/08G11C16/3459
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Quick Facts
Patent No.
US 12712024
App. No.
18/935,014
Granted
Aug 18, 2026
Kind
B2
Abstract

The present application discloses a memory, a memory operation method and a memory system. The memory includes: a memory array and a peripheral circuit, wherein the memory array includes a plurality of memory cells coupled to a first bit line and to a plurality of word lines respectively, wherein the plurality of word lines include a selected word line coupled to a memory cell to be programmed; the peripheral circuit is configured to: apply precharge voltages to the plurality of word lines; sequentially reduce the precharge voltages applied to the plurality of word lines to a first turn-off voltage according to the arrangement order of the memory cells coupled to the plurality of word lines in the memory array; apply a program voltage to a selected word line in the plurality of word lines, and apply a turn-on voltage to other word lines in the plurality of word lines.

Claims (63)

1 . A memory comprising:

a memory array comprising a plurality of memory cells coupled to a first bit line and to a plurality of word lines respectively, wherein the plurality of word lines comprises a selected word line coupled to a memory cell to be programmed; and

a peripheral circuit configured to:

apply precharge voltages to the plurality of word lines;

sequentially reduce the precharge voltages applied to the plurality of word lines to a first turn-off voltage according to an arrangement order of memory cells coupled to the plurality of word lines in the memory array;

apply a program voltage to the selected word line in the plurality of word lines; and

apply a turn-on voltage to other word lines besides the selected word line in the plurality of word lines.

2 . The memory of claim 1 , wherein the peripheral circuit is further configured to:

apply the first turn-off voltage to the plurality of word lines one by one according to the arrangement order of the memory cells coupled to the plurality of word lines in the memory array.

3 . The memory of claim 2 , wherein the peripheral circuit is further configured to:

obtain group configuration information of the plurality of word lines, the group configuration information including a plurality of groups which the plurality of word lines are divided into, wherein at least two word lines in a same group of the plurality of groups are arranged consecutively in the memory array; and

sequentially apply the first turn-off voltage to the word lines in each of the plurality of groups according to the arrangement order of the memory cells coupled to the plurality of word lines in the memory array.

4 . The memory of claim 1 , wherein the peripheral circuit is further configured to:

sequentially reduce the precharge voltages applied to the plurality of word lines to a first intermediate voltage according to the arrangement order of the memory cells coupled to the plurality of word lines in the memory array, wherein the first intermediate voltage is between the precharge voltages and the first turn-off voltage; and

sequentially reduce the first intermediate voltage applied to the plurality of word lines to the first turn-off voltage according to the arrangement order of the memory cells coupled to the plurality of word lines in the memory array.

5 . The memory of claim 1 , wherein the peripheral circuit is further configured to:

sequentially reduce the precharge voltages applied to the plurality of word lines to the first turn-off voltage along a direction from a drain select gate to a source select gate.

6 . The memory of claim 1 , wherein,

the plurality of word lines include a deselected word line coupled to a programmed memory cell.

7 . The memory of claim 1 , wherein the peripheral circuit is further configured to:

apply a verification voltage to the selected word line in the plurality of word lines, and apply a read voltage to the other word lines in the plurality of word lines; and

sequentially apply a second turn-off voltage to the plurality of word lines according to the arrangement order of the memory cells coupled to the plurality of word lines in the memory array.

8 . The memory of claim 7 , wherein the peripheral circuit is further configured to:

sequentially reduce at least one of the verification voltage and the read voltage to a second intermediate voltage according to the arrangement order of the memory cells coupled to the plurality of word lines in the memory array, wherein the second intermediate voltage is either between the verification voltage and the second turn-off voltage or between the read voltage and the second turn-off voltage; and

sequentially reduce the second intermediate voltage applied to the plurality of word lines to the second turn-off voltage according to the arrangement order of the memory cells coupled to the plurality of word lines in the memory array.

9 . The memory of claim 1 , wherein the peripheral circuit is further configured to:

sequentially reduce the precharge voltages applied to a portion of the plurality of word lines to the first turn-off voltage with a preset word line interval according to the arrangement order of the memory cells coupled to the plurality of word lines in the memory array.

10 . The memory of claim 9 , wherein the peripheral circuit is further configured to:

determine a plurality of target word lines from the plurality of word lines according to a preset interval algorithm, wherein two target word lines of the plurality of target word lines are separated with at least one word line; and

sequentially reduce the precharge voltages applied to the plurality of target word lines to the first turn-off voltage according to the arrangement order of the memory cells coupled to the plurality of target word lines in the memory array.

11 . The memory of claim 1 , wherein the peripheral circuit is further configured to:

after the first turn-off voltage is applied to the plurality of word lines, apply the program voltage to the selected word line in the plurality of word lines, and apply the turn-on voltage to the other word lines in the plurality of word lines at the same time.

12 . A method of programming a memory, comprising:

applying precharge voltages to a plurality of word lines;

sequentially reducing the precharge voltages applied to the plurality of word lines to a first turn-off voltage according to an arrangement order of memory cells coupled to the plurality of word lines in a memory array;

applying a program voltage to a selected word line in the plurality of word lines; and

applying a turn-on voltage to other word lines besides the selected word line in the plurality of word lines.

13 . The method of claim 12 , wherein sequentially reducing the precharge voltages applied to the plurality of word lines to the first turn-off voltage according to the arrangement order of memory cells coupled to the plurality of word lines in the memory array comprises:

applying the first turn-off voltage to the plurality of word lines one by one according to the arrangement order of the memory cells coupled to the plurality of word lines in the memory array.

14 . The method of claim 12 , wherein sequentially reducing the precharge voltages applied to the plurality of word lines to the first turn-off voltage according to the arrangement order of memory cells coupled to the plurality of word lines in the memory array comprises applying the first turn-off voltage to the plurality of word lines in groups according to the arrangement order of the memory cells coupled to the plurality of word lines in the memory array, and wherein applying the first turn-off voltage to the plurality of word lines in groups according to the arrangement order of the memory cells coupled to the plurality of word lines in the memory array comprises:

obtaining group configuration information of the plurality of word lines, the group configuration information including a plurality of groups which the plurality of word lines are divided into, wherein at least two word lines in a same group of the plurality of groups are arranged consecutively in the memory array; and

sequentially applying the first turn-off voltage to word lines in each of the plurality of groups according to the arrangement order of the memory cells coupled to the plurality of word lines in the memory array.

15 . The method of claim 12 , wherein sequentially reducing the precharge voltages applied to the plurality of word lines to the first turn-off voltage according to the arrangement order of memory cells coupled to the plurality of word lines in the memory array comprises:

sequentially reducing the precharge voltages applied to the plurality of word lines to a first intermediate voltage according to the arrangement order of the memory cells coupled to the plurality of word lines in the memory array, wherein the first intermediate voltage is between the precharge voltages and the first turn-off voltage; and

sequentially reducing the first intermediate voltage applied to the plurality of word lines to the first turn-off voltage according to the arrangement order of the memory cells coupled to the plurality of word lines in the memory array.

16 . The method of claim 12 , wherein sequentially reducing the precharge voltages applied to the plurality of word lines to the first turn-off voltage according to the arrangement order of memory cells coupled to the plurality of word lines in the memory array comprises:

sequentially reducing the precharge voltages applied to the plurality of word lines to the first turn-off voltage along a direction from a source select gate to a drain select gate.

17 . The method of claim 12 , wherein

the selected word line is coupled to a memory cell to be programmed and a deselected word line is coupled to a programmed memory cell.

18 . The method of claim 12 , further comprising:

applying a verification voltage to the selected word line in the plurality of word lines, and applying a read voltage to the other word lines in the plurality of word lines; and

sequentially applying a second turn-off voltage to the plurality of word lines according to the arrangement order of the memory cells coupled to the plurality of word lines in the memory array.

19 . The method of claim 12 , wherein sequentially reducing the precharge voltages applied to the plurality of word lines to the first turn-off voltage according to the arrangement order of memory cells coupled to the plurality of word lines in the memory array comprises:

sequentially reducing the precharge voltages applied to a portion of the plurality of word lines to the first turn-off voltage with a preset word line interval according to the arrangement order of the memory cells coupled to the plurality of word lines in the memory array.

20 . A memory system, comprising:

one or more memories comprising:

a memory array comprising a plurality of memory cells coupled to a first bit line and to a plurality of word lines respectively, wherein the plurality of word lines comprises a selected word line coupled to a memory cell to be programmed; and

a peripheral circuit configured to:

apply precharge voltages to the plurality of word lines;

sequentially reduce the precharge voltages applied to the plurality of word lines to a first turn-off voltage according to an arrangement order of memory cells coupled to the plurality of word lines in the memory array;

apply a program voltage to the selected word line in the plurality of word lines; and

apply a turn-on voltage to other word lines besides the selected word line in the plurality of word lines; and

a memory controller coupled to the one or more memories and configured to control the one or more memories.