Semiconductor memory device
A semiconductor memory device includes conductive layers stacked in a stacking direction and extending in a first direction intersecting the stacking direction, semiconductor columns extending in the stacking direction and facing the conductive layers, charge storage films provided between the conductive layers and the semiconductor columns, first and second wirings provided on one side in the stacking direction with respect to the conductive layers, arranged in the first direction, and electrically connected to the semiconductor columns, sense amplifier units electrically connected to the first wirings, and a node electrically and commonly connected to the second wirings. One of the sense amplifier units is electrically connected to K1 number of first wirings (where K1 is an integer of 1 or more). The node is electrically connected to K number of second wirings (where K2 is an integer of 2 or more and is greater than K1).
1 . A semiconductor memory device comprising:
a substrate;
a plurality of conductive layers stacked in a stacking direction intersecting a surface of the substrate, and extending in a first direction intersecting the stacking direction;
a plurality of semiconductor columns extending in the stacking direction and facing the plurality of conductive layers;
a plurality of charge storage films provided between the plurality of conductive layers and the plurality of semiconductor columns;
a plurality of first and second wirings provided on one side in the stacking direction with respect to the plurality of conductive layers, arranged in the first direction, and electrically connected to the plurality of semiconductor columns;
a plurality of sense amplifier units electrically connected to the plurality of first wirings;
a memory hole region in which the plurality of semiconductor columns are provided in a regular pattern; and
a node electrically and commonly connected to the plurality of second wirings,
wherein one of the plurality of sense amplifier units is electrically connected to K1 first wirings (where K1 is an integer of 1 or more), and
the node is electrically connected to K2 second wirings (where K2 is an integer of 2 or more and is greater than K1), and
the memory hole region includes
a first range provided between a first boundary line provided on an inner side of the memory hole region from one end portion of the memory hole region in the first direction, and a second boundary line provided on an inner side of the memory hole region from the other end portion of the memory hole region in the first direction,
a second range provided between the one end portion of the memory hole region in the first direction and the first boundary line, and
a third range provided between the other end portion of the memory hole region in the first direction and the second boundary line, and
the plurality of first wirings are provided in the first range, and the plurality of second wirings are provided in one or both of the second range and the third range.
2 . The semiconductor memory device according to claim 1 ,
wherein the node is electrically connected to the plurality of second wirings without a switching element therebetween.
3 . The semiconductor memory device according to claim 1 , further comprising:
a first transistor that is electrically and commonly connected to the plurality of second wirings through the node.
4 . The semiconductor memory device according to claim 3 , further comprising:
an external pad electrode that is electrically connected to the plurality of second wirings through the first transistor.
5 . The semiconductor memory device according to claim 4 ,
wherein the external pad electrode is used to supply a ground voltage.
6 . The semiconductor memory device according to claim 4 ,
wherein a voltage of an internal node other than the node is measurable through the external pad electrode.
7 . The semiconductor memory device according to claim 3 , further comprising:
a current measurement circuit that is electrically connected to the plurality of second wirings through the first transistor.
8 . The semiconductor memory device according to claim 7 ,
wherein each of the plurality of sense amplifier units includes a data latch circuit, and
the current measurement circuit does not include a data latch circuit.
9 . The semiconductor memory device according to claim 1 , further comprising:
a plurality of second transistors electrically connected to the plurality of second wirings,
wherein the node is electrically and commonly connected to the plurality of second wirings through the plurality of second transistors.
10 . The semiconductor memory device according to claim 9 ,
wherein gate electrodes of the plurality of second transistors are electrically and commonly connected.
11 . The semiconductor memory device according to claim 9 , further comprising:
an external pad electrode that is electrically connected to the plurality of second wirings through the plurality of second transistors.
12 . The semiconductor memory device according to claim 11 ,
wherein the external pad electrode is used to supply a ground voltage.
13 . The semiconductor memory device according to claim 11 ,
wherein a voltage of an internal node other than the node is measurable through the external pad electrode.
14 . The semiconductor memory device according to claim 9 , further comprising:
a current measurement circuit that is electrically connected to the plurality of second wirings through the plurality of second transistors.
15 . The semiconductor memory device according to claim 14 ,
wherein each of the plurality of sense amplifier units includes a data latch circuit, and
the current measurement circuit does not include a data latch circuit.
16 . The semiconductor memory device according to claim 1 , further comprising:
a plurality of contact electrodes that extend in the stacking direction and are connected to the plurality of conductive layers,
wherein the plurality of second wirings are provided between the plurality of first wirings and the plurality of contact electrodes when viewed from above.
17 . A semiconductor memory device comprising:
a substrate;
a plurality of conductive layers stacked in a stacking direction intersecting a surface of the substrate, and extending in a first direction intersecting the stacking direction;
a plurality of semiconductor columns extending in the stacking direction and facing the plurality of conductive layers;
a plurality of charge storage films provided between the plurality of conductive layers and the plurality of semiconductor columns;
a plurality of first and second wirings provided on one side in the stacking direction with respect to the plurality of conductive layers, arranged in the first direction, and electrically connected to the plurality of semiconductor columns;
a sense amplifier unit electrically connected to one of the first wirings; and
a current measurement circuit electrically connected to one of the second wirings,
wherein the sense amplifier unit includes a data latch circuit, and
the current measurement circuit does not include a data latch circuit.
18 . A semiconductor memory device comprising:
a substrate;
a plurality of conductive layers stacked in a stacking direction intersecting a surface of the substrate, and extending in a first direction intersecting the stacking direction;
a plurality of semiconductor columns extending in the stacking direction and facing the plurality of conductive layers;
a plurality of charge storage films provided between the plurality of conductive layers and the plurality of semiconductor columns;
a plurality of wirings provided on one side in the stacking direction with respect to the plurality of conductive layers, arranged in the first direction, and electrically connected to the plurality of semiconductor columns;
a memory hole region in which the plurality of semiconductor columns are provided in a regular pattern; and
a node electrically and commonly connected to a subset of the plurality of wirings,
wherein the node is electrically connected to the plurality of wirings of the subset without providing a switching element therebetween, and
the memory hole region includes
a first range provided between a first boundary line provided on an inner side of the memory hole region from one end portion of the memory hole region in the first direction, and a second boundary line provided on an inner side of the memory hole region from the other end portion of the memory hole region in the first direction,
a second range provided between the one end portion of the memory hole region in the first direction and the first boundary line, and
a third range provided between the other end portion of the memory hole region in the first direction and the second boundary line, and
the subset of the plurality of wirings is provided in one or both of the second range and the third range and another subset of the plurality of wirings is provided in the first range.
19 . The semiconductor memory device according to claim 18 , further comprising:
a plurality of sense amplifier units electrically connected to said another subset of the plurality of wirings.