Memory system and operating method thereof with tracking array to adjust sensing time for accuracy

1 . An operating method of a memory system, comprising:

inputting tracking data into a tracking array;

generating a plurality of tracking logic values by a plurality of tracking cell columns in the tracking array according to the tracking data;

counting the plurality of tracking logic values to generate a summation value;

adjusting a sensing time of a sensing device according to the summation value;

performing a computing operation by a computing array to generate a plurality of computing signals;

sensing the plurality of computing signals by the sensing device according to the adjusted sensing time and a clock signal;

when the summation value is different from a preset value, adjusting a period of the clock signal;

setting the sensing time as a first sensing time;

generating a plurality of tracking signals according to the tracking data by the plurality of tracking cell columns;

sensing the plurality of tracking signals according to the first sensing time to generate a plurality of first tracking logic values;

counting the plurality of first tracking logic values to generate a first summation value;

when the first summation value is equal to a quantity of the plurality of tracking cell columns, setting the sensing time as a second sensing time,

wherein the second sensing time is smaller than the first sensing time;

sensing the plurality of tracking signals according to the second sensing time to generate a plurality of second tracking logic values;

counting the plurality of second tracking logic values to generate a second summation value;

when the second summation value is different from the quantity of the plurality of tracking cell columns, setting the sensing time as the first sensing time;

sensing the plurality of computing signals according to the first sensing time by the sensing device;

before setting the sensing time as the first sensing time, setting the sensing time as an initial sensing time;

sensing the plurality of tracking signals according to the initial sensing time to generate a plurality of initial tracking logic values;

counting the plurality of initial tracking logic values to generate an initial summation value; and

when the initial summation value is equal to the quantity of the plurality of tracking cell columns, setting the sensing time as a third sensing time,

wherein the third sensing time is smaller than the initial sensing time, and

a difference between the third sensing time and the initial sensing time is equal to a difference between the first sensing time and the second sensing time.

2 . The operating method of claim 1 , wherein adjusting the sensing time of the sensing device according to the summation value comprises:

comparing the summation value and a quantity of the plurality of tracking cell columns;

when the summation value is different from the quantity of the plurality of tracking cell columns, adjusting the sensing time; and

when the summation value is equal to the quantity of the plurality of tracking cell columns, determining the sensing time.

3 . The operating method of claim 1 , wherein each of tracking bits of the tracking data has the same logic value.

4 . A memory system, comprising:

a plurality of tracking cell columns configured to generate a plurality of tracking logic values according to tracking data;

a computing array configured to generate a plurality of computing signals; and

a sensing device configured to sense the plurality of computing signals according to a clock signal,

wherein the sensing device comprises a segment circuit configured to count the plurality of tracking logic values to generate a summation value,

when the summation value is different from a preset value, a period of the clock signal is adjusted, and

when the summation value is equal to the preset value, the period of the clock signal is determined for sensing the plurality of computing signals,

wherein the preset value is a quantity of the plurality of tracking cell columns.

5 . The memory system of claim 4 , wherein reference data bits stored in each tracking cell column of the plurality of tracking cell columns has P first logic value, and P is a positive integer.

6 . The memory system of claim 4 , further comprising:

a tracking array comprising the plurality of tracking cell columns, and configured to store a plurality of tracking bits,

wherein along a direction, a quantity of a first logic value of the plurality of tracking bits is increased gradually.

7 . The memory system of claim 6 , wherein along the direction, a quantity of a second logic value of the plurality of tracking bits is decreased gradually, and

the first logic value is different from the second logic value.