Memory system
A memory system includes a semiconductor memory including a plurality of first memory cells each configured to store data in a non-volatile manner according to a threshold voltage, and a controller. The controller is configured to perform a first error correction process for the plurality of first memory cells, based on first hard bit data and first soft bit data acquired using a plurality of first soft bit voltages that have been calculated based on a shift voltage, and to correct the shift voltage when a condition based on correction data generated during the first error correction process, is satisfied.
1 . A memory system comprising:
a semiconductor memory including a plurality of first memory cells each configured to store data in a non-volatile manner according to a threshold voltage; and
a controller that stores a first shift voltage, wherein
the controller is configured to:
perform a first error correction process for the plurality of first memory cells, based on first hard bit data and first soft bit data acquired using a plurality of first soft bit voltages that have been calculated based on the first shift voltage, and generate a channel matrix that indicates, for each of a plurality of threshold voltage ranges, a number of first memory cells determined to store a first value and a number of first memory cells determined to store a second value,
determine whether a hard error condition is satisfied based on a number of first memory cells indicated by the generated channel matrix to be in a hard error state, wherein a first memory cell is in the hard error state when a threshold voltage of the first memory cell is lower than a lowest voltage among the plurality of first soft bit voltages or higher than a highest voltage among the plurality of first soft bit voltages, and
when the hard error condition is satisfied, calculate a second shift voltage based on the channel matrix and update the first shift voltage stored in the controller with the second shift voltage for use in a next execution of the first error correction process.
2 . The memory system according to claim 1 , wherein
the semiconductor memory further includes a plurality of second memory cells each configured to store data in a non-volatile manner according to a threshold voltage, and
the controller is configured to perform a second error correction process for the plurality of second memory cells, based on second hard bit data and second soft bit data acquired using a plurality of second soft bit voltages that have been calculated based on the second shift voltage.
3 . The memory system according to claim 2 , wherein the first hard bit data is acquired using a first hard bit voltage that is greater than a first voltage having a lowest voltage among the plurality of first soft bit voltages and less than a second voltage having a highest voltage among the plurality of first soft bit voltages.
4 . The memory system according to claim 3 , wherein the second hard bit data is acquired using a second hard bit voltage that is different from the first hard bit voltage.
5 . The memory system according to claim 1 , wherein
the controller calculates the second shift voltage and updates the first shift voltage when the first error correction process completes successfully.
6 . The memory system according to claim 5 , wherein
the controller calculates, based on a result of the first error correction process, a first quantity of first memory cells determined to store the first value and having a threshold voltage that is lower than the lowest voltage among the plurality of first soft bit voltages, and
the hard error condition is satisfied if the first quantity is one or more.
7 . The memory system according to claim 3 , wherein
the controller calculates, based on a result of the first error correction process, a first quantity of first memory cells determined to store the second value and having a threshold voltage that is higher than the highest voltage among the plurality of first soft bit voltages, and
the hard error condition is satisfied if the first quantity is one or more.
8 . A memory system comprising:
a semiconductor memory including a plurality of first memory cells each configured to store data in a non-volatile manner according to a threshold voltage; and
a controller that stores a first shift voltage and a second shift voltage, wherein
the controller is configured to:
perform a first error correction process for the plurality of first memory cells, based on first hard bit data that is acquired using a first hard bit voltage and first soft bit data acquired using a plurality of first soft bit voltages that are less than the first hard bit voltage, which have been calculated based on the first shift voltage, and a plurality of second soft bit voltages that are greater than the first hard bit voltage, which have been calculated based on the second shift voltage, and generate a channel matrix that indicates, for each of a plurality of threshold voltage ranges, a number of first memory cells determined to store a first value and a number of first memory cells determined to store a second value,
determine whether each of a first hard error condition and a second hard error condition is satisfied based on a number of first memory cells indicated by the generated channel matrix to be in a hard error state, wherein a first memory cell is in the hard error state when a threshold voltage of the first memory cell is less than a lowest voltage among the plurality of first soft bit voltages or higher than a highest voltage among the plurality of second soft bit voltages, and
when the first hard error condition is satisfied, correct the first shift voltage, and when the second hard error condition is satisfied, correct the second shift voltage, for use in a next execution of the first error correction process.
9 . The memory system according to claim 8 , wherein
each of the first soft bit voltages is less than the first hard bit voltage by an integer multiple of the first shift voltage, and
each of the second soft bit voltages is greater than the first hard bit voltage by an integer multiple of the second shift voltage.
10 . The memory system according to claim 9 , wherein
the corrected first shift voltage is larger than the first shift voltage, and the corrected second shift voltage is larger than the second shift voltage.
11 . The memory system according to claim 9 , wherein
the controller is configured to correct the first shift voltage and the second shift voltage, when the first error correction process completes successfully.
12 . The memory system according to claim 11 , wherein
the controller calculates, based on a result of the first error correction process, a first quantity of first memory cells determined to store the first value and having a threshold voltage that is lower than the lowest voltage among the plurality of first soft bit voltages, a second quantity of first memory cells determined to store the second value and having a threshold voltage that is higher than the highest voltage among the plurality of second soft bit voltages, and
the first hard error condition is satisfied when the first quantity is one or more, and
the second hard error condition is satisfied when the second quantity is one or more.
13 . The memory system according to claim 12 , wherein
the first hard error condition is satisfied when the first quantity is equal to or more than a first reference quantity, and
the second hard error condition is satisfied when the second quantity is equal to or more than a second reference quantity.
14 . The memory system according to claim 13 , wherein
the controller corrects the first shift voltage based on a quantity of first memory cells determined to store the first value in each of a plurality of threshold voltage ranges that are defined by the first soft bit voltages, the first hard bit voltage, and the second soft bit voltages between the lowest voltage among the plurality of first soft bit voltages and the highest voltage among the plurality of second soft bit voltages, and
the controller corrects the second shift voltage based on a quantity of first memory cells determined to store the second value in each of the plurality of threshold voltage ranges.
15 . The memory system according to claim 14 , wherein
the controller corrects the first shift voltage such that a quantity of first memory cells determined to store the first value and having a threshold voltage that is less than a lowest of a plurality of third soft bit voltages that are calculated using the corrected first shift voltage is zero, and
the controller corrects the second shift voltage such that a quantity of first memory cells determined to store the second value and having a threshold voltage that is greater than a highest of a plurality of fourth soft bit voltages that are calculated using the corrected second shift voltage is zero.
16 . The memory system according to claim 11 , wherein
the controller calculates, based on a result of the first error correction process, a first quantity of first memory cells determined to store the first value and having a threshold voltage that is lower than the lowest voltage among the plurality of first soft bit voltages, a second quantity of first memory cells determined to store the second value and having a threshold voltage that is higher than the highest voltage among the plurality of second soft bit voltages, and
the first hard error condition is satisfied when a first proportion for the first quantity is equal to or greater than a first reference proportion, and
the second hard error condition is satisfied when a second proportion for the second quantity is equal to or greater than a second reference proportion.
17 . The memory system according to claim 16 , wherein
the first proportion is a proportion of the first quantity to a quantity of first memory cells determined to store the first value and having a threshold voltage that is lower than the first hard bit voltage, and
the second proportion is a proportion of the second quantity to a quantity of first memory cells determined to store the second value and having a threshold voltage that is equal to or higher than the first hard bit voltage.
18 . The memory system according to claim 17 , wherein
the controller corrects the first shift voltage according to a magnitude of the first proportion, and
the controller corrects the second shift voltage according to a magnitude of the second proportion.
19 . The memory system according to claim 11 , wherein
the controller is configured to calculate at least one of a third shift voltage that is different from the first shift voltage and the corrected first shift voltage, and a fourth shift voltage that is different from the second shift voltage and the corrected second shift voltage, when the first error correction process does not complete successfully, and
the controller is configured to perform a second error correction process for the plurality of first memory cells, based on second hard bit data that is acquired using a second hard bit voltage that is different from the first hard bit voltage and second soft bit data acquired using a plurality of third soft bit voltages, which have been calculated based on at least one of the third shift voltage and the fourth shift voltage.
20 . The memory system according to claim 8 , wherein
the semiconductor memory further includes
a first word line connected to the plurality of first memory cells, and
a plurality of second memory cells each configured to store data in a non-volatile manner according to a threshold voltage and connected to the first word line together with the plurality of first memory cells, and
the first hard bit data and the first soft bit data each include data for the first memory cells and data for the second memory cells.