Apparatus and methods for in-place read refresh for nonvolatile memory devices
The memory device includes a memory block with an array of memory cells that are arranged in a plurality of word lines. The memory cells are programmed to one bit per memory cell with each memory cell being either in an erased data state or a programmed data state. The memory device also includes circuitry that is configured to determine that the memory cells have experienced significant read disturb. Without erasing the memory cells, the circuitry is further configured to program the memory cells in the programmed data state directly to higher threshold voltages to increase a threshold voltage margin between the memory cells in the erased data state and the memory cells in the programmed data state.
1 . A method of operating a memory device, comprising steps of:
providing a memory device that includes a memory block with an array of memory cells that are arranged in a plurality of word lines, the memory cells being programmed to one bit per memory cell with each memory cell being either in an erased data state or a programmed data state;
determining that the memory cells have experienced significant read disturb;
without erasing the memory cells, programming the memory cells in the programmed data state directly to higher threshold voltages to increase a threshold voltage margin between the memory cells in the erased data state and the memory cells in the programmed data state; and
setting a reference voltage SLCR for use during read operations from a first level to a higher second level following the step of programming the memory cells in the programmed data state directly to the higher threshold voltages.
2 . The method as set forth in claim 1 , further including steps of counting a number of read cycles to establish a read cycle count; and
comparing the read cycle count to a predetermined threshold; and
wherein the step of determining that the memory cells have experienced significant read disturb occurs in response to the read cycle count exceeding the predetermined threshold.
3 . The method as set forth in claim 1 wherein the step of programming the memory cells in the programmed data state directly to the higher threshold voltages includes:
applying a programming voltage to a selected word line;
setting a plurality of bit lines that are electrically coupled with the memory cells of the selected word line and that are in the programmed data state at very low voltages; and
setting a plurality of bit lines that are electrically coupled with the memory cells of the selected word line and that are in the erased data state at inhibit voltages.
4 . The method as set forth in claim 1 , wherein the step of programming the memory cells in the programmed data state directly to the higher threshold voltages includes a single programming pulse and no verify operations or includes multiple programming pulses and verify operations.
5 . A method of operating a memory device, comprising steps of:
providing a memory device that includes a memory block with an array of memory cells that are arranged in a plurality of word lines, the memory cells being programmed to one bit per memory cell with each memory cell being either in an erased data state or a programmed data state;
determining that the memory cells have experienced significant read disturb;
without erasing the memory cells, programming the memory cells in the programmed data state directly to higher threshold voltages to increase a threshold voltage margin between the memory cells in the erased data state and the memory cells in the programmed data state; and
wherein the step of determining that the memory cells have experienced significant read disturb occurs in response to a determination that a count of memory cells in a voltage range that is below a voltage range associated with the programmed data state is greater than a predetermined threshold.
6 . A memory device, comprising:
a memory block with an array of memory cells that are arranged in a plurality of word lines, the memory cells being programmed to one bit per memory cell with each memory cell being either in an erased data state or a programmed data state; and circuitry configured to:
determine that the memory cells have experienced significant read disturb;
without erasing the memory cells, program the memory cells in the programmed data state directly to higher threshold voltages to increase a threshold voltage margin between the memory cells in the erased data state and the memory cells in the programmed data state, and
set a reference voltage SLCR for use during read operations from a first level to a higher second level after programming the memory cells in the programmed data state directly to the higher threshold voltages.
7 . The memory device as set forth in claim 6 , wherein the circuitry is configured to count a number of read cycles to establish a read cycle count; and
compare the read cycle count to a predetermined threshold; and
wherein the circuitry determines that the memory cells have experienced significant read disturb in response to the read cycle count exceeding the predetermined threshold.
8 . The memory device as set forth in claim 6 wherein when programming the memory cells in the programmed data state directly to the higher threshold voltages, the circuitry:
applies a programming voltage to a selected word line;
sets a plurality of bit lines that are electrically coupled with the memory cells of the selected word line and that are in the programmed data state at very low voltages; and
sets a plurality of bit lines that are electrically coupled with the memory cells of the selected word line and that are in the erased data state at inhibit voltages.
9 . The memory device as set forth in claim 6 , wherein the circuitry is configured to count a number of memory cells that have threshold voltages in a voltage range that is below a voltage range associated with the programmed data state,
compare the count of memory cells that have threshold voltages in the voltage range that is below the voltage range associated with the programmed data state to a predetermined threshold, and
determine that the memory cells have experienced significant read disturb in response to the count of memory cells being greater than the predetermined threshold.
10 . The memory device as set forth in claim 6 , wherein when programming the memory cells in the programmed data state directly to the higher threshold voltages, the circuitry applies a single programming pulse to a selected word line without a following verify operation or applies multiple programming pulses to the selected word line with following verify operations.
11 . A computing system, comprising:
a processor unit;
a plurality of flash memory packages in electrical communication with the processor unit;
at least one of the flash memory packages including a memory block with an array of memory cells that are arranged in a plurality of word lines, the memory cells being programmed to one bit per memory cell with each memory cell being either in an erased data state or a programmed data state; and
the at least one of the flash memory packages further including circuitry that is configured to:
determine that the memory cells have experienced significant read disturb,
without erasing the memory cells, program the memory cells in the programmed data state directly to higher threshold voltages to increase a threshold voltage margin between the memory cells in the erased data state and the memory cells in the programmed data state, and
set a reference voltage SLCR for use during read operations from a first level to a higher second level after programming the memory cells in the programmed data state directly to the higher threshold voltages.
12 . The computing system as set forth in claim 11 , wherein the circuitry is configured to count a number of read cycles to establish a read cycle count; and
compare the read cycle count to a predetermined threshold; and
wherein the circuitry determines that the memory cells have experienced significant read disturb in response to the read cycle count exceeding the predetermined threshold.
13 . The computing system as set forth in claim 11 , wherein when programming the memory cells in the programmed data state directly to the higher threshold voltages, the circuitry:
applies a programming voltage to a selected word line;
sets a plurality of bit lines that are electrically coupled with the memory cells of the selected word line and that are in the programmed data state at very low voltages; and
sets a plurality of bit lines that are electrically coupled with the memory cells of the selected word line and that are in the erased data state at inhibit voltages.
14 . The computing system as set forth in claim 11 , wherein the circuitry is configured to count a number of memory cells that have threshold voltages in a voltage range that is below a voltage range associated with the programmed data state,
compare the count of memory cells that have threshold voltages in the voltage range that is below the voltage range associated with the programmed data state to a predetermined threshold, and
determine that the memory cells have experienced significant read disturb in response to the count of memory cells being greater than the predetermined threshold.
15 . The computing system as set forth in claim 11 , wherein the plurality of flash memory packages are able to electrically communicate with the processor unit at rates of greater than 3 TB/s.
16 . The computing system as set forth in claim 11 , wherein the flash memory packages receive supply voltages that are no greater than 1.2 V.
17 . The computing system as set forth in claim 11 , wherein when programming the memory cells in the programmed data state directly to the higher threshold voltages, the circuitry applies a single programming pulse to a selected word line without a following verify operation or applies multiple programming pulses to the selected word line with verify operations.