IP Library › Granted Patent US 12712035
Granted Patent B2
US 12712035 · App. 18/785,866 · Granted Aug 18, 2026

Predictive program verification

Inventors: Jungmi Ko (Santa Clara, CA); Junghwan Lee (Cupertino, CA); Byungkwan Jeong (San Jose, CA); Kwangho Baek (Sunnyvale, CA); Seong Je Park (San Jose, CA)
Assignee: Micron Technology, Inc.
G11C16/3459G11C16/102G11C16/24
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Quick Facts
Patent No.
US 12712035
App. No.
18/785,866
Granted
Aug 18, 2026
Kind
B2
Abstract

A memory array comprises a plurality of memory cells. Control logic coupled to the memory array can cause a program voltage to be applied to a subset of the plurality of memory cells to be programmed to a specified logical level, where the specified logical level is associated with a group of logical levels. The control logic can cause a first program verify voltage associated with the group of logical levels to be applied to the memory cells. The control logic can decrement a count associated with the group of logical levels, where the count indicates a number of remaining program voltages to be applied for programming the subset of memory cells to a logical level of the predefined group of logical levels and terminate the program operation for the subset of plurality of memory cells responsive to determine that the count falls below a threshold value.

Claims (53)

1 . A memory device comprising:

a memory array comprising a plurality of memory cells; and

control logic, operatively coupled with the memory array, to perform operations comprising:

causing a program voltage to be applied to a subset of the plurality of memory cells to be programmed to a specified logical level during a program operation, wherein the specified logical level is associated with a predefined group of logical levels, wherein each respective logical level is associated with a corresponding program verify voltage of a plurality of program verify voltages, and wherein a first program verify voltage associated with the group of logical levels has a smallest magnitude among the plurality of program verify voltages;

causing the first program verify voltage associated with the group of logical levels to be applied to the subset of memory cells;

responsive to applying the first program verify voltage, decrementing a count associated with the specified logical level, wherein the count indicates a number of remaining program voltages to be applied for programming the subset of memory cells to the specified logical level of the predefined group of logical levels; and

responsive to determining that the count falls below a threshold value, terminating the program operation for the subset of the plurality of memory cells.

2 . The memory device of claim 1 , wherein the operations further comprise:

causing a second program voltage to be applied to a second subset of the plurality of memory cells to be programmed to a second specified logical level, wherein the second specified logical level is associated with the group of logical levels;

causing the first program verify voltage associated with the group of logical levels to be applied to the second subset of the plurality of memory cells;

responsive to applying the first program verify voltage, decrementing a second count associated with the second specified logical level, wherein the second count indicates a number of remaining program voltages to be applied for programming the second subset of memory cells to the second specified logical level of the predefined group of logical levels; and

responsive to determining that the second count falls below a second threshold value, terminating the program operation for the second subset of the plurality of memory cells.

3 . The memory device of claim 1 , wherein the count associated with the specified logical level is stored in a page buffer coupled to a bitline connected to the subset of memory cells.

4 . The memory device of claim 1 , wherein the operations comprise:

decrement a count associated with each of the logical levels of the predefined group of logical levels responsive to causing the first program verify voltage to be applied.

5 . The memory device of claim 1 , wherein the operations further comprise:

causing a second program voltage to be applied to a second subset of the plurality of memory cells to be programmed to a second specified logical level during the program operation, wherein the second specified logical level is associated with a second group of logical levels;

causing a second program verify voltage associated with the second group of logical levels to be applied to the second subset of the plurality of memory cells;

responsive to applying the second program verify voltage, decrementing a second count associated with the second specified logical level, wherein the second count indicates a second number of remaining program voltages to be applied to the second subset of memory cells to the second specified logical level of the second group of logical levels; and

responsive to determining that the second count exceeds a second threshold value, continuing the program operation for the second subset of the plurality of memory cells.

6 . The memory device of claim 5 , wherein a number of logical levels in the group of logical levels is equal to a number of logical levels in the second group of logical levels.

7 . The memory device of claim 1 , wherein the memory cells are quad-level cells (QLC).

8 . A method, comprising:

causing a program voltage to be applied to a subset of a plurality of memory cells to be programmed to a specified logical level during a program operation, wherein the specified logical level is associated with a predefined group of logical levels, wherein each respective logical level is associated with a corresponding program verify voltage of a plurality of program verify voltages, and wherein a first program verify voltage associated with the group of logical levels has a smallest magnitude among the plurality of program verify voltages;

causing the first program verify voltage associated with the group of logical levels to be applied to the subset of memory cells; and

responsive to applying the first program verify voltage, decrementing a count associated with the specified logical level, wherein the count indicates a number of remaining program voltages to be applied for programming the subset of memory cells to the specified logical level of the predefined group of logical levels; and

responsive to determining that the count falls below a threshold value, terminating the program operation for the subset of the plurality of memory cells.

9 . The method of claim 8 , further comprising:

causing a second program voltage to be applied to a second subset of the plurality of memory cells to be programmed to a second specified logical level, wherein the second specified logical level is associated with the group of logical levels;

causing the first program verify voltage associated with the group of logical levels to be applied to the second subset of the plurality of memory cells;

responsive to applying the first program verify voltage, decrementing a second count associated with the second specified logical level, wherein the second count indicates a number of remaining program voltages to be applied for programming the second subset of memory cells to the second specified logical level of the predefined group of logical levels; and

responsive to determining that the second count falls below a second threshold value, terminating the program operation for the second subset of the plurality of memory cells.

10 . The method of claim 8 , wherein the count associated with the specified logical level is stored in a page buffer coupled to a bitline connected to the subset of memory cells.

11 . The method of claim 8 , further comprising:

decrementing a count associated with each of the logical levels of the predefined group of logical levels responsive to causing the first program verify voltage to be applied.

12 . The method of claim 8 , further comprising:

causing a second program voltage to be applied to a second subset of the plurality of memory cells to be programmed to a second specified logical level during the program operation, wherein the second specified logical level is associated with a second group of logical levels;

causing a second program verify voltage associated with the second group of logical levels to be applied to the second subset of the plurality of memory cells;

responsive to applying the second program verify voltage, decrementing a second count associated with the second specified logical level, wherein the second count indicates a second number of remaining program voltages to be applied to the second subset of memory cells to the second specified logical level of the second group of logical levels;

responsive to determining that the second count exceeds a second threshold value, continuing the program operation for the second subset of the plurality of memory cells.

13 . The method of claim 12 , wherein a number of logical levels in the group of logical levels is equal to a number of logical levels in the second group of logical levels.

14 . The method of claim 8 , wherein the memory cells are quad-level cells (QLC).

15 . A non-transitory computer-readable medium comprising executable instructions which when executed by a processing device, cause the processing device to:

cause a program voltage to be applied to a subset of a plurality of memory cells to be programmed to a specified logical level during a program operation, wherein the specified logical level is associated with a predefined group of logical levels, wherein each respective logical level is associated with a corresponding program verify voltage of a plurality of program verify voltages, and wherein a first program verify voltage associated with the group of logical levels has a smallest magnitude among the plurality of program verify voltages;

cause the first program verify voltage associated with the group of logical levels to be applied to the subset of memory cells; and

responsive to applying the first program verify voltage, decrement a count associated with the specified logical level, wherein the count indicates a number of remaining program voltages to be applied for programming the subset of memory cells to the specified logical level of the predefined group of logical levels; and

responsive to determining that the count falls below a threshold value, terminate the program operation for the subset of the plurality of memory cells.

16 . The non-transitory computer-readable medium of claim 15 , further comprising executable instructions which when executed by the processing device, cause the processing device to:

cause a second program voltage to be applied to a second subset of the plurality of memory cells to be programmed to a second specified logical level, wherein the second specified logical level is associated with the group of logical levels;

cause the first program verify voltage associated with the group of logical levels to be applied to the second subset of the plurality of memory cells;

responsive to applying the first program verify voltage, decrement a second count associated with the second specified logical level, wherein the second count indicates a number of remaining program voltages to be applied for programming the second subset of memory cells to the second specified logical level of the predefined group of logical levels; and

responsive to determining that the second count falls below a second threshold value, terminate the program operation for the second subset of the plurality of memory cells.

17 . The non-transitory computer-readable medium of claim 15 , wherein the count associated with the specified logical level is stored in a page buffer coupled to a bitline connected to the subset of memory cells.