IP Library › Granted Patent US 12712037

Granted Patent B2

US 12712037 · App. 18/425,383 · Granted Aug 18, 2026

Selective data pattern write scrub for a memory system

Inventors: Zhongguang Xu (San Jose, CA); Murong Lang (San Jose, CA); Zhenming Zhou (San Jose, CA)

Assignee: Micron Technology, Inc.

G11C16/3495 G11C16/3404

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Quick Facts

Patent No.: US 12712037
App. No.: 18/425,383
Granted: Aug 18, 2026
Kind: B2

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Abstract

A system includes a memory device having a plurality of memory cells and a processing device operatively coupled to the memory device. The processing device is to determine to perform a rewrite on at least a portion of the plurality of memory cells. The processing device can determine that a number of rewrite operations at first subset of memory cells storing a first logic state fail to satisfy a threshold criterion. The processing device can also cause a rewrite of data stored at a second subset of memory cells storing a second logic state in response to determining the number of rewrite operations performed at the first subset of memory cells fail to satisfy the threshold criterion.

Claims (60)

1 . A system comprising:

a memory device comprising a plurality of memory cells, wherein a first subset of the plurality of memory cells store a first logic state and a second subset of the plurality of memory cells store a second logic state; and

a processing device operatively coupled to the memory device, the processing device to perform operations comprising:

determining to perform a rewrite operation on at least a portion of the plurality of memory cells;

determining a threshold criterion based on a maximum operational voltage of the plurality of memory cells, wherein the threshold criterion comprises a number of scrub cycles for which the processing device is to refrain from rewriting data stored at the first subset of the plurality of memory cells;

determining that a number of rewrite operations performed at the second subset of the plurality of memory cells fail to satisfy the threshold criterion based on comparing the number of rewrite operations performed to the threshold criterion; and

responsive to determining that the number of rewrite operations performed at the second subset of the plurality of memory cells fail to satisfy the threshold criterion, causing a rewrite of data stored at the second subset of the plurality of memory cells while refraining from rewriting data stored at the first subset of the plurality of memory cells.

2 . The system of claim 1 , wherein the operations further comprise:

determining a rate of voltage drift at the plurality of memory cells; and

responsive to determining the rate of voltage drift at the plurality of memory cells, adjusting the threshold criterion based on the rate of voltage drift.

3 . The system of claim 1 , wherein the operations further comprise:

determining a number of program/erase cycles performed by the plurality of memory cells; and

responsive to determining the number of program/erase cycles performed by the plurality of memory cells, adjusting the threshold criterion based on the number of program/erase cycles.

4 . The system of claim 1 , wherein the operations further comprise:

responsive to determining to perform the rewrite on at least the portion of the plurality of memory cells, incrementing a counter of the number of rewrite operations performed at the second subset of memory cells by a first value; and

decrementing the counter of the number of rewrite operations performed at the second subset of memory cells by a second value based at least in part on rewriting the data stored at the first subset of the plurality of memory cells.

5 . The system of claim 1 , wherein the operations further comprise:

responsive to determining that the number of rewrite operations performed at the second subset of the plurality of memory cells satisfy the threshold criterion, causing a rewrite of data stored at the first subset of the plurality of memory cells; and

6 . The system of claim 1 , wherein causing the rewrite of data stored at the second subset of the plurality of memory cells comprise:

causing a first write operation to be performed and write a first logic state to the second subset of the plurality of memory cells; and

causing a second write operation to be performed and write a second logic state to the second subset of the plurality of memory cells.

7 . The system of claim 1 , wherein causing the rewrite of data stored at the second subset of the plurality of memory cells comprise:

causing a first write operation to be performed and write a first logic state to the second subset of the plurality of memory cells.

8 . The system of claim 1 , wherein the operations further comprise:

causing a read operation to be performed at the plurality of memory cells; and

responsive to the read operation, determining the first subset of the plurality of memory cells and the second subset of the plurality of memory cells.

9 . A method comprising:

determining, by a processing device, to perform a rewrite operation on at least a portion of a plurality of memory cells of a memory device, wherein a first subset of the plurality of memory cells store a first logic state and a second subset of the plurality of memory cells store a second logic state;

10 . The method of claim 9 , wherein the operations further comprise:

determining a rate of voltage drift at the plurality of memory cells; and

responsive to determining the rate of voltage drift at the plurality of memory cells, adjusting the threshold criterion based on the rate of voltage drift.

11 . The method of claim 9 , wherein the operations further comprise:

determining a number of program/erase cycles performed by the plurality of memory cells; and

responsive to determining the number of program/erase cycles performed by the plurality of memory cells, adjusting the threshold criterion based on the number of program/erase cycles.

12 . The method of claim 9 , wherein the operations further comprise:

13 . The method of claim 9 , wherein the operations further comprise:

14 . The method of claim 9 , wherein causing the rewrite of data stored at the second subset of the plurality of memory cells comprise:

causing a first write operation to be performed and write a first logic state to the second subset of the plurality of memory cells; and

causing a second write operation to be performed and write a second logic state to the second subset of the plurality of memory cells.

15 . The method of claim 9 , wherein causing the rewrite of data stored at the second subset of the plurality of memory cells comprise:

causing a first write operation to be performed and write a first logic state to the second subset of the plurality of memory cells.

16 . The method of claim 9 , wherein the operations further comprise:

causing a read operation to be performed at the plurality of memory cells; and

responsive to the read operation, determining the first subset of the plurality of memory cells and the second subset of the plurality of memory cells.

17 . A non-transitory computer-readable medium storing instructions, which when executed by a processing device that is operatively coupled with a memory device, performing a plurality of operations comprising:

determining to perform a rewrite operation on at least a portion of a plurality of memory cells of a memory device, wherein a first subset of the plurality of memory cells store a first logic state and a second subset of the plurality of memory cells store a second logic state;

18 . The non-transitory computer-readable medium of claim 17 , wherein the plurality of operations further comprises:

determining a rate of voltage drift at the plurality of memory cells; and

responsive to determining the rate of voltage drift at the plurality of memory cells, adjusting the threshold criterion based on the rate of voltage drift.