Defect detection during erase operations
A system includes a memory device including a memory array and processing logic, operatively coupled with the memory array, to perform operations including initiating an erase operation performed with respect to the memory array, identifying, between a pair of components of the memory array, at least one current differential indicative of at least one defect with respect to at least one failure point of the memory array, and causing an indication of the at least one defect to be generated. The erase operation includes a select gate scan sub-operation.
1 . A memory device comprising:
a memory array; and
processing logic, operatively coupled with the memory array, to perform operations comprising:
initiating an erase operation performed with respect to the memory array, wherein the erase operation comprises a select gate scan sub-operation;
identifying, between a pair of components of the memory array, at least one current differential indicative of at least one defect with respect to at least one failure point of the memory array; and
causing an indication of the at least one defect to be generated.
2 . The memory device of claim 1 , wherein the erase operation further comprises an erase pulse sub-operation and an erase verify sub-operation.
3 . The memory device of claim 2 , wherein the erase operation further comprises a pre-programming sub-operation performed prior to the erase pulse sub-operation.
4 . The memory device of claim 2 , wherein the erase operation further comprises an anneal pulse sub-operation performed between the erase pulse sub-operation and the erase verify sub-operation.
5 . The memory device of claim 2 , wherein the operations further comprise:
determining that the erase verify sub-operation is successful; and
in response to determining that the erase verify sub-operation is successful, causing the select gate scan sub-operation to be performed.
6 . The memory device of claim 1 , wherein:
the at least one current differential is identified as a difference between a first voltage applied to a first component of the pair of components, and a second voltage applied to a second component of the pair of components; and
determining whether the at least one current differential is indicative of at least one defect with respect to the at least one failure point of the memory array comprises determining whether the at least one current differential exceeds a corresponding threshold current differential.
7 . The memory device of claim 6 , wherein:
the pair of components comprises at least one of: a wordline (WL), a pillar, a through-array-via, a bitline, a source line, or a select gate; and
the at least one failure point comprises at least one of: a WL to WL leak, a WL to pillar leak or short, a WL to TAV leak or short, a source line leak, a bitline leak, a pillar to WL and select gate (SG) leak, or a WL to bitline or source line short.
8 . The memory device of claim 1 , wherein the operations further comprise causing at least one remedial action to be performed, the at least one remedial action comprising at least one of: marking the memory device as a defective memory device, or discarding the defective memory device.
9 . A method comprising:
initiating, by a processing device, an erase operation performed with respect to a memory array of a memory device, wherein the erase operation comprises a select gate scan sub-operation;
identifying, by the processing device and between a pair of components of the memory array, at least one current differential indicative of at least one defect with respect to at least one failure point of the memory array; and
causing, by the processing device, an indication of the at least one defect to be generated.
10 . The method of claim 9 , wherein the erase operation further comprises an erase pulse sub-operation and an erase verify sub-operation.
11 . The method of claim 10 , wherein the erase operation further comprises a pre-programming sub-operation performed prior to the erase pulse sub-operation.
12 . The method of claim 10 , wherein the erase operation further comprises an anneal pulse sub-operation performed between the erase pulse sub-operation and the erase verify sub-operation.
13 . The method of claim 10 , further comprising:
determining, by the processing device, that the erase verify sub-operation is successful; and
in response to determining that the erase verify sub-operation is successful, causing, by the processing device, the select gate scan sub-operation to be performed.
14 . The method of claim 9 , wherein:
the at least one current differential is identified as a difference between a first voltage applied to a first component of the pair of components, and a second voltage applied to a second component of the pair of components; and
determining whether the at least one current differential is indicative of at least one defect with respect to the at least one failure point of the memory array comprises determining whether the at least one current differential exceeds a corresponding threshold current differential.
15 . The method of claim 9 , wherein:
the pair of components comprises at least one of: a wordline (WL), a pillar, a through-array-via, a bitline, a source line, or a select gate; and
the at least one failure point comprises at least one of: a WL to WL leak, a WL to pillar leak or short, a WL to TAV leak or short, a source line leak, a bitline leak, a pillar to WL and select gate (SG) leak, or a WL to bitline or source line short.
16 . The method of claim 9 , further comprising causing, by the processing device, at least one remedial action to be performed, the at least one remedial action comprising at least one of: marking the memory device as a defective memory device, or discarding the defective memory device.
17 . A system comprising:
a memory comprising instructions; and
processing logic, operatively coupled with the memory, to perform operations comprising:
sending, to a memory device, a request to initiate an erase operation performed with respect to a memory array of the memory device, wherein the erase operation comprises a select gate scan sub-operation;
receiving, from the memory device, an indication of at least one defect with respect to at least one failure point of the memory array, wherein the at least one defect corresponds at least one current differential identified between a pair of components of the memory array; and
in response to receiving the indication of the at least one defect, sending, to the memory device, a request to perform at least one remedial action.
18 . The system of claim 17 , wherein:
the at least one current differential is identified as a difference between a first voltage applied to a first component of the pair of components, and a second voltage applied to a second component of the pair of components; and
the at least one current differential exceeds a corresponding threshold current differential.
19 . The system of claim 17 , wherein:
the pair of components comprises at least one of: a wordline (WL), a pillar, a through-array-via, a bitline, a source line, or a select gate; and
the at least one failure point comprises at least one of: a WL to WL leak, a WL to pillar leak or short, a WL to TAV leak or short, a source line leak, a bitline leak, a pillar to WL and select gate (SG) leak, or a WL to bitline or source line short.
20 . The system of claim 17 , wherein the at least one remedial action comprises at least one of: marking the memory device as a defective memory device, or discarding the defective memory device.