Voltage scaling based on error rate

1 . A method, comprising:

reading a codeword from a memory device in response to a read operation;

generating, by circuitry resident on the memory device, parity information;

appending, by the circuitry, the parity information to the codeword read from the memory device to generate a bit string comprising the codeword read from the memory device and the parity information;

transmitting the bit string from the memory device to a physical input/output (PHY I/O) device external to the memory device and coupled thereto via a channel;

determining, utilizing parity logic resident on the PHY I/O, a parity mismatch value by comparing the parity information transmitted from the memory device to parity information calculated by parity logic of the PHY I/O, wherein the parity mismatch value indicates an actual bit-error-rate (BER) of the channel; and

comparing, the determined parity mismatch value to a target parity mismatch value, wherein the target parity mismatch value is determined based on a difference between a target total BER associated with the memory device and an actual total BER associated with the memory device, and wherein the actual total BER associated with the memory device comprises:

the actual BER of the channel, which is based on bit errors occurring in association with transmitting the bit string from the memory device to the PHY/IO device external to the memory device; and

an actual memory device BER, which is based on bit errors occurring prior to the parity information being appended to the codeword read from the memory device.

2 . The method of claim 1 , wherein:

the circuitry resident on the memory device is resident on a memory die associated with the memory device, and

the circuitry generates the parity information on the memory die.

3 . The method of claim 1 , wherein the codeword comprises user data and error correction data.

4 . The method of claim 1 , further comprising appending, by the circuitry, respective parity information to a plurality of respective codewords read from the memory device to generate a plurality of bit strings comprising the respective codewords read from the memory device and the respective parity information.

5 . The method of claim 1 , further comprising generating the parity information and appending the parity information to the codeword read from the memory device to generate the bit string without enabling a memory controller coupled to the memory device.

6 . The method of claim 1 , further comprising, utilizing a decoder external to the memory device to:

decode the codeword received in the bit string to determine the actual total BER; and

calculate the actual memory device BER based on a difference between the actual total BER and the actual BER of the channel.

7 . An apparatus, comprising:

a plurality of memory dice of a memory device; and

circuitry resident on at least one of the plurality of memory dice, wherein the circuitry is configured to:

generate parity information;

concatenate the parity information to a codeword read from one of the plurality of memory dice to generate a bit string including the codeword and the concatenated parity information; and

cause the bit string to be transferred to circuitry external to the plurality of memory dice;

wherein the circuitry external to the plurality of memory dice comprises a physical input/output (PHY I/O) device couplable to the plurality of memory dice via a channel; wherein parity logic resident on the PHY I/O is utilized to:

determine a parity mismatch value based on bit values contained within the bit string, wherein the parity mismatch value indicates an actual bit-error-rate (BER) of the channel; and

compare the determined parity mismatch value to a target parity mismatch value, wherein the target parity mismatch value is determined based on a difference between a target total BER associated with the memory device and an actual total BER associated with the memory device and wherein the actual total BER associated with the memory device comprises:

the actual BER of the channel, which is based on bit errors occurring in association with transmitting the bit string from the memory device to the PHY I/O device external to the memory device; and

an actual memory device BER, which is based on bit errors occurring prior to the parity information being appended to the codeword read from the memory device.

8 . The apparatus of claim 7 , wherein the plurality of memory dice are resident on a NAND memory device.

9 . A system, comprising:

a memory device comprising a plurality of memory dice, wherein the memory device is configured to:

generate, by circuitry resident on at least one of the plurality of memory dice, parity information;

append, by the circuitry, the parity information to data read from one of the plurality of memory dice to generate a bit string, the bit string comprising the data read from the one of the plurality of memory dice and the parity information; and

transmit the bit string, from the memory device to a physical input/output (PHY I/O) device external to the memory device and coupled thereto via a channel; and

the PHY I/O device including parity logic resident on the PHY I/O, wherein the parity logic is configured to:

receive the bit string, provided from the memory device over the channel;

determine bit values contained within the received bit string; and

determine parity information transmitted from the memory device based on the bit values contained within the received bit string;

calculate a parity mismatch value based on the bit values contained within the received bit string, wherein the parity mismatch value indicates an actual bit-error-rate (BER) of the channel; and

compare the calculated parity mismatch value to a target parity mismatch value, wherein the target parity mismatch value is determined based on a difference between a target total BER associated with the memory device and an actual total BER associated with a memory device, and wherein the actual total BER associated with the memory device comprises:

the actual BER of the channel, which is based on bit errors occurring in association with transmitting the bit string from the memory device to the PHY I/O device external to the memory device; and

an actual memory device BER, which is based on bit errors occurring prior to the parity information being appended to the codeword read from the memory device.

10 . The system of claim 9 , further comprising the circuitry resident on one of the plurality of memory dice generating the parity information and appending the parity information to the data read from one of the plurality of memory dice to generate the bit string without enabling a memory controller coupled to the memory device.

11 . The system of claim 9 , wherein the bit string further includes a codeword and a decoder external to the memory device is further configured to determine an actual total BER associated with a total BER based on the data in the codeword.

12 . The system of claim 11 , wherein the parity logic is further configured to:

utilize a decoder external to the memory device to decode data in a codeword received in the bit string;

determine an actual total BER based on the data in the codeword; and

calculate the actual memory device BER based on a difference between the actual total BER and the actual BER of the channel.

13 . The system of claim 9 , wherein calculating the parity mismatch value comprises comparing the bit values contained within the parity information in the received bit string to parity information calculated by the parity logic resident on the PHY I/O device.