Dual-read data integrity scan in a memory sub-system

1 . A system comprising:

a memory device;

a processing device, operatively coupled with the memory device, to perform operations comprising:

performing a first data integrity scan on a block of the memory device to determine a first combined reliability statistic of memory cells in the block associated with a first program level and a second program level;

performing, using a predetermined read level offset corresponding to one of the first program level or the second program level, a second data integrity scan on the block of the memory device to determine a second combined reliability statistic of the memory cells in the block associated with the first program level and the second program level, wherein performing the second data integrity scan comprises applying a modified first read voltage to memory cells corresponding to the first program level and applying an unmodified second read voltage to memory cells corresponding to the second program level;

determining a difference between the first combined reliability statistic and the second combined reliability statistic, wherein the difference is attributable to the first program level; and

responsive to the difference between the first combined reliability statistic and the second combined reliability statistic satisfying a threshold criterion, performing a corrective action on the block of the memory device.

2 . The system of claim 1 , wherein the processing device is to perform operations further comprising:

detecting an occurrence of a data integrity check trigger event; and

performing the first data integrity scan responsive to the occurrence of the data integrity check trigger event.

3 . The system of claim 1 , wherein the first data integrity scan is performed using default read voltages corresponding to the first program level and the second program level, and wherein the first data integrity scan comprises at least one of a lower-page read operation or an extra-page read operation.

4 . The system of claim 1 , wherein the processing device is to perform operations further comprising:

determining whether the first combined reliability statistic satisfies a scan threshold criterion; and

performing the second data integrity scan responsive to the first combined reliability statistic satisfying the scan threshold criterion.

5 . The system of claim 1 , wherein performing the second data integrity scan comprises:

applying the modified first read voltage to memory cells corresponding to the first program level, wherein the modified first read voltage comprises a first read voltage applied during the first data integrity scan modified by the predetermined read level offset; and

applying the unmodified second read voltage to memory cells corresponding to the second program level, wherein the unmodified second read voltage comprises a same read voltage applied during the first data integrity scan.

6 . The system of claim 1 , wherein the first data integrity scan and the second data integrity scan comprise read disturb scans, and wherein the corrective action comprises folding data in the block to another block of the memory device.

7 . The system of claim 1 , wherein the first data integrity scan and the second data integrity scan comprise program completion scans, and wherein the corrective action comprises marking the block for garbage collection and reprogramming data from the block to another block of the memory device.

8 . A method comprising:

performing a first data integrity scan on a block of a memory device to determine a first combined reliability statistic of memory cells in the block associated with a first program level and a second program level;

performing, using a predetermined read level offset corresponding to one of the first program level or the second program level, a second data integrity scan on the block of the memory device to determine a second combined reliability statistic of the memory cells in the block associated with the first program level and the second program level, wherein performing the second data integrity scan comprises applying a modified first read voltage to memory cells corresponding to the first program level and applying an unmodified second read voltage to memory cells corresponding to the second program level;

determining a difference between the first combined reliability statistic and the second combined reliability statistic, wherein the difference is attributable to the first program level; and

responsive to the difference between the first combined reliability statistic and the second combined reliability statistic satisfying a threshold criterion, performing a corrective action on the block of the memory device.

9 . The method of claim 8 , further comprising:

detecting an occurrence of a data integrity check trigger event; and

performing the first data integrity scan responsive to the occurrence of the data integrity check trigger event.

10 . The method of claim 8 , wherein the first data integrity scan is performed using default read voltages corresponding to the first program level and the second program level, and wherein the first data integrity scan comprises at least one of a lower-page read operation or an extra-page read operation.

11 . The method of claim 8 , further comprising:

determining whether the first combined reliability statistic satisfies a scan threshold criterion; and

performing the second data integrity scan responsive to the first combined reliability statistic satisfying the scan threshold criterion.

12 . The method of claim 8 , wherein performing the second data integrity scan comprises:

applying the modified first read voltage to memory cells corresponding to the first program level, wherein the modified first read voltage comprises a first read voltage applied during the first data integrity scan modified by the predetermined read level offset; and

applying the unmodified second read voltage to memory cells corresponding to the second program level, wherein the unmodified second read voltage comprises a same read voltage applied during the first data integrity scan.

13 . The method of claim 8 , wherein the first data integrity scan and the second data integrity scan comprise read disturb scans, and wherein the corrective action comprises folding data in the block to another block of the memory device.

14 . The method of claim 8 , wherein the first data integrity scan and the second data integrity scan comprise program completion scans, and wherein the corrective action comprises marking the block for garbage collection and reprogramming data from the block to another block of the memory device.

15 . A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:

performing a first data integrity scan on a block of a memory device to determine a first combined reliability statistic of memory cells in the block associated with a first program level and a second program level;

performing, using a predetermined read level offset corresponding to one of the first program level or the second program level, a second data integrity scan on the block of the memory device to determine a second combined reliability statistic of the memory cells in the block associated with the first program level and the second program level, wherein performing the second data integrity scan comprises applying a modified first read voltage to memory cells corresponding to the first program level and applying an unmodified second read voltage to memory cells corresponding to the second program level;

determining a difference between the first combined reliability statistic and the second combined reliability statistic, wherein the difference is attributable to the first program level; and

responsive to the difference between the first combined reliability statistic and the second combined reliability statistic satisfying a threshold criterion, performing a corrective action on the block of the memory device.

16 . The non-transitory computer-readable storage medium of claim 15 , wherein the instructions cause the processing device to perform operations further comprising:

detecting an occurrence of a data integrity check trigger event; and

performing the first data integrity scan responsive to the occurrence of the data integrity check trigger event.

17 . The non-transitory computer-readable storage medium of claim 15 , wherein the first data integrity scan is performed using default read voltages corresponding to the first program level and the second program level, and wherein the first data integrity scan comprises at least one of a lower-page read operation or an extra- page read operation.

18 . The non-transitory computer-readable storage medium of claim 15 , wherein the instructions cause the processing device to perform operations further comprising:

determining whether the first combined reliability statistic satisfies a scan threshold criterion; and

performing the second data integrity scan responsive to the first combined reliability statistic satisfying the scan threshold criterion.

19 . The non-transitory computer-readable storage medium of claim 15 , wherein performing the second data integrity scan comprises:

applying the modified first read voltage to memory cells corresponding to the first program level, wherein the modified first read voltage comprises a first read voltage applied during the first data integrity scan modified by the predetermined read level offset; and

applying the unmodified second read voltage to memory cells corresponding to the second program level, wherein the unmodified second read voltage comprises a same read voltage applied during the first data integrity scan.

20 . The non-transitory computer-readable storage medium of claim 15 , wherein the first data integrity scan and the second data integrity scan comprise at least one of read disturb scans or program completion scans, and wherein the corrective action comprises at least one of folding data in the block to another block of the memory device or marking the block for garbage collection and reprogramming data from the block to another block of the memory device.