Variable resistance for current control in nonvolatile memory arrays

1 . An apparatus, comprising:

one or more control circuit configured to connect to a nonvolatile memory cell structure that includes nonvolatile memory cells each having a programmable resistive element, the one or more control circuit configured to:

receive an address that corresponds to a location in the nonvolatile memory cell structure;

set a variable resistor according to the location, the variable resistor connected in series with conductive lines connected to a selected nonvolatile memory cell that is located at the location, the variable resistor set such that the sum of the resistance of the conductive lines and the variable resistor is within a predetermined range; and

drive a memory access current through the selected nonvolatile memory cell, the conductive lines and the variable resistor in series.

2 . The apparatus of claim 1 , wherein the one or more control circuit is connected to a memory controller and is configured to receive the address from the memory controller in a command from the memory controller.

3 . The apparatus of claim 2 , wherein the command is a write command to write data at the location in the nonvolatile memory and the memory access current is a write current.

4 . The apparatus of claim 1 , wherein the one or more control circuit is configured to set the variable resistor to a resistance value that depends on the location such that the resistance value for locations corresponding to higher combined word line resistance and bit line resistance is a lower resistance value and the resistance value for locations with lower combined word line resistance and bit line resistance is set to a higher resistance value such that the sum of the resistance of the conductive lines and the variable resistor is constant.

5 . The apparatus of claim 4 , wherein the higher combined word line resistance and bit line resistance in series with the lower resistance value is substantially equal to the lower combined word line resistance and bit line resistance in series with the higher resistance value.

6 . The apparatus of claim 5 , wherein the locations corresponding to higher combined word line resistance and bit line resistance are located in one or more corner area of the nonvolatile memory cell structure and the locations corresponding to lower combined word line resistance and bit line resistance are located in a central area of the nonvolatile memory cell structure.

7 . The apparatus of claim 1 , wherein the variable resistor includes a plurality of switchable resistors connected in parallel between a driver circuit and a word line or bit line of the nonvolatile memory cell structure.

8 . The apparatus of claim 1 , wherein the nonvolatile memory cell structure includes a plurality of word lines extending along a word line direction, a plurality of bit lines extending along a bit line direction that is perpendicular to the word line direction, a plurality of nonvolatile memory cells extending vertically, each nonvolatile memory cell connected between a respective word line and a respective word line.

9 . The apparatus of claim 8 , wherein each nonvolatile memory cell includes a selector connected in series with the programmable resistive element.

10 . A method, comprising:

receiving a plurality of addresses corresponding to a plurality of locations in a cross-point Magnetoresistive Random Access Memory (MRAM) structure that includes word lines extending along a first direction and bit lines extending along a second direction that is perpendicular to the first direction;

setting a plurality of variable resistors, the variable resistors connected in series with selected nonvolatile memory cells at the locations and in series with word lines and bit lines connected to the selected nonvolatile memory cells, each variable resistor set to a respective resistance value that depends on a location of a selected nonvolatile memory cell with which it is connected such that, for each location, the sum of resistance of the connected word line, bit line and the variable resistor is within a predetermined range; and

driving memory access currents through the selected nonvolatile memory cells in series with connected word and bit lines and the variable resistors.

11 . The method of claim 10 , wherein each variable resistor is set to a respective value that depends on the location of the selected nonvolatile memory cell with which it is connected such that series resistance of respective word line, bit line and variable resistor is substantially equal for each selected nonvolatile memory cell.

12 . The method of claim 10 , wherein driving the memory access currents includes driving substantially equal memory access currents through each of the selected nonvolatile memory cells.

13 . The method of claim 10 , wherein setting the plurality of variable resistors includes, for each variable resistor, enabling only selected resistors from a plurality of resistors connected in parallel.

14 . The method of claim 13 , wherein setting the plurality of variable resistors includes checking each address against a record that indicates corresponding resistors to select.

15 . The method of claim 10 , further comprising:

measuring temperature at a location at or near the cross-point MRAM structure; and

setting the plurality of variable resistors to the respective resistance values according to the locations and the temperature.

16 . The method of claim 10 , further comprising:

testing a die that includes the MRAM structure to determine respective resistance values for the locations; and

storing the respective resistance values for the die in the die.

17 . The method of claim 16 , further comprising:

subsequent to storing the respective resistance values, using the respective resistance values for memory access operations for a first period of time;

subsequently, repeating testing of the die to determine new respective resistance values for the locations;

storing the new respective resistance values in the die; and

subsequently using the new respective resistance values for a second period of time.

18 . A system, comprising:

a nonvolatile memory cell structure that includes nonvolatile memory cells each having a programmable resistive element, each nonvolatile memory cell connected to a corresponding word line and a corresponding bit line; and

means for setting a variable resistor to a resistance value selected according to a location in the nonvolatile memory cell structure of a nonvolatile memory cell to be accessed such that, for each location in the nonvolatile memory cell structure, the sum of resistance of the connected word line, bit line and the variable resistor is within a predetermined range and accessing the nonvolatile memory cell by passing a current through the variable resistor in series with the nonvolatile memory cell and the connected word line and bit line.

19 . The system of claim 18 , further comprising a temperature measurement circuit that is connected to the means for setting the variable resistor to provide a temperature measurement to the means for setting the variable resistor for use in selecting the resistance value.

20 . The system of claim 18 , wherein the nonvolatile memory cell structure is located on a memory die and the means for setting the variable resistor is located on a control die that is bonded to the memory die.