Memory devices using defective address information processing circuits, and operating methods, and memory systems thereof

1 . A memory device, comprising:

a first defective address information memory, wherein the first defective address information memory is configured to store multiple pieces of initial defective address information, and the multiple pieces of initial defective address information comprise initial target defective address information and multiple pieces of initial non-target defective address information, the initial target defective address information being stored in the first defective address information memory after the multiple pieces of initial non-target defective address information;

a defective address information processing circuit, wherein the defective address information processing circuit is connected to the first defective address information memory, and is configured to:

compare the initial target defective address information previously stored in the first defective address information memory with each of the multiple pieces of initial non-target defective address information previously stored in the first defective address information memory;

control whether to process the initial non-target defective address information based on a comparison result, wherein respective comparing sub-circuits of the defective address information processing circuit are configured to operate in parallel to output respective sub-comparison results, and the comparison result is generated based on the respective sub-comparison results;

in response to one of the sub-comparison results indicating a match between the initial target defective address information and a respective one of the multiple pieces of initial non-target defective address information, generating corresponding defective address information comprising second identification information that comprises a second value, the second value indicating that a corresponding relationship between a defective address and a redundant address in the corresponding defective address information is invalid, and the corresponding defective address information is prohibited to be used; and

output multiple pieces of defective address information corresponding to the multiple pieces of initial defective address information; and

a second defective address information memory, wherein the second defective address information memory is connected to the defective address information processing circuit, and is configured to store the multiple pieces of defective address information.

2 . The memory device of claim 1 , wherein:

each of the multiple pieces of initial defective address information comprises first identification information, the first identification information indicates whether corresponding initial defective address information comprises a defective address and a redundant address corresponding to the defective address, and each of the multiple pieces of defective address information comprises a defective address, the second identification information, and a redundant address corresponding to the defective address.

3 . The memory device of claim 2 , wherein the defective address information processing circuit is further configured to:

determine whether the defective address in the initial target defective address information is the same as the defective address in the initial non-target defective address information;

in response to the defective address in the initial target defective address information being different from the defective address in the initial non-target defective address information, configure the second identification information as a first value for the corresponding defective address information, the first value included in the second identification information indicating that the corresponding relationship between the defective address and the redundant address in the corresponding defective address information is valid; and

in response to the defective address in the initial target defective address information being the same as the defective address in the initial non-target defective address information, configure the second identification information as the second value for the corresponding defective address information.

4 . The memory device of claim 2 , wherein the defective address information processing circuit is configured to:

determine whether the defective address in the initial target defective address information is the same as the defective address in the initial non-target defective address information;

in response to the defective address in the initial target defective address information being different from the defective address in the initial non-target defective address information, configure the second identification information in the defective address information to have a first value corresponding to the first identification information in the initial non-target defective address information; and

in response to the defective address in the initial target defective address information being the same as the defective address in the initial non-target defective address information, modify the first identification information in the initial non-target defective address information to generate the second identification information having the second value for the defective address information.

5 . The memory device of claim 2 , wherein:

the defective address information processing circuit comprises a comparing circuit and an identification modifying circuit,

the comparing circuit is connected to the first defective address information memory and is configured to compare the defective address in the initial target defective address information with the defective address in the initial non-target defective address information, and output the comparison result, and

the identification modifying circuit is connected to the comparing circuit and is configured to configure the second identification information for the corresponding defective address information based on the comparison result.

6 . The memory device of claim 5 , wherein:

the comparing circuit comprises a plurality of comparing sub-circuits, each of the comparing sub-circuits is connected to the first defective address information memory and is configured to compare the initial target defective address information and one piece of multiple pieces of initial non-target defective address information and output a sub-comparison result of the sub-comparison results; and

the identification modifying circuit comprises a plurality of identification modifying sub-circuits, each of the identification modifying sub-circuits is connected to one of the plurality of comparing sub-circuits and the first defective address information memory, and is configured to configure the second identification information for the corresponding defective address information based on the sub-comparison result.

7 . The memory device of claim 6 , wherein the comparing sub-circuit comprises an exclusive OR gate.

8 . The memory device of claim 6 , wherein:

the defective address information processing circuit further comprises a buffer, and

the buffer is connected to the first defective address information memory, each of the comparing sub-circuits, and the second defective address information memory, and is configured to store the initial target defective address information.

9 . The memory device of claim 8 , wherein:

the first defective address information memory comprises a plurality of first memory areas arranged in sequence,

a first one of the first memory areas is connected to the buffer and is configured to store the initial target defective address information,

each first memory area, other than the first one of the first memory areas, is connected to one of the comparing sub-circuits, and each first memory area, other than the first one of the first memory areas, is configured to store the initial non-target defective address information,

the second defective address information memory comprises a plurality of second memory areas arranged in sequence,

a first one of the second memory areas is connected to the buffer and is configured to store the initial target defective address information, and

each second memory area, other than the first one of the second memory areas, is connected to one of the identification modifying sub-circuits.

10 . The memory device of claim 9 , wherein:

the second defective address information memory is further connected to the first defective address information memory,

the memory device further comprises a determining circuit connected to the first defective address information memory and the defective address information processing circuit, and

the determining circuit is configured to:

determine whether a defective address and a redundant address corresponding to the defective address are stored in the first one of the first memory areas according to the first identification information in the first one of the first memory areas, and output a determination result;

in response to the determination result indicating that the defective address and the redundant address corresponding to the defective address are not stored in the first one of the first memory areas, prohibit the defective address information processing circuit from modifying the initial non-target defective address information, the initial non-target defective address information being directly output to the second defective address information memory as defective address information; and

in response to the determination result indicating that the defective address and the redundant address corresponding to the defective address are stored in the first one of the first memory areas, enable the defective address information processing circuit to modify the initial non-target defective address information.

11 . The memory device of claim 1 , wherein a redundant address in the initial target defective address information comprises a post-encapsulation repair redundant address, and a redundant address in the initial non-target defective address information comprises a pre-encapsulation repair redundant address.

12 . The memory device of claim 1 , wherein the memory device comprises a three-dimensional dynamic random access memory device.

13 . A method of operating a memory device, wherein the memory device comprises:

a first defective address information memory configured to store multiple pieces of initial defective address information, and the multiple pieces of initial defective address information comprise initial target defective address information and multiple pieces of initial non-target defective address information, the initial target defective address information being stored in the first defective address information memory after the multiple pieces of initial non-target defective address information; and

a defective address information processing circuit coupled to the first defective address information memory;

the method comprising:

comparing, through the defective address information processing circuit, the initial target defective address information with each piece of the multiple pieces of initial non-target defective address information;

generating, through respective comparing sub-circuits of the defective address information processing circuit configured to operate in parallel, respective sub-comparison results, and controlling whether to process the initial non-target defective address information based on a comparison result, the comparison result comprising the respective sub-comparison results;

in response to one of the sub-comparison results indicating a match between the initial target defective address information and a respective one of the initial non-target defective address information, generating corresponding defective address information comprising second identification information that comprises a second value, the second value indicating that a corresponding relationship between a defective address and a redundant address in the corresponding defective address information is invalid, and the corresponding defective address information is prohibited to be used; and

outputting, through the defective address information processing circuit, multiple pieces of defective address information corresponding to the multiple pieces of initial defective address information, and storing, in a second defective address information memory coupled to the defective address information processing circuit, the multiple pieces of defective address information.

14 . The method of claim 13 , wherein:

each of the multiple pieces of initial defective address information comprises first identification information, the first identification information indicates whether a corresponding initial defective address information comprises a defective address and a redundant address corresponding to the defective address, and

each of the multiple pieces of defective address information comprises a defective address, the second identification information, and a redundant address corresponding to the defective address.

15 . The method of claim 14 , further comprising:

comparing the defective address in the initial target defective address information with the defective address in the initial non-target defective address information and outputting the comparison result, comprising:

comparing the initial target defective address information with one piece of the multiple pieces of initial non-target defective address information at each time and outputting the corresponding sub-comparison result.

16 . The method of claim 14 , wherein determining whether to process the initial non-target defective address information based on the comparison result and outputting the multiple pieces of defective address information corresponding to the multiple pieces of initial defective address information comprises:

determining whether the defective address in the initial target defective address information is the same as the defective address in the initial non-target defective address information;

in response to the defective address in the initial target defective address information being different from the defective address in the initial non-target defective address information, configuring the second identification information as a first value for the corresponding defective address information, the first value included in the second identification information indicates that the corresponding relationship between the defective address and the redundant address in the corresponding defective address information is valid; and

in response to the defective address in the initial target defective address information being the same as the defective address in the initial non-target defective address information, configuring the second identification information as the second value for the corresponding defective address information.

17 . The method of claim 13 , wherein the memory device comprises a three-dimensional dynamic random access memory device.

18 . The memory device of claim 1 , wherein:

the second defective address information memory is configured to store the multiple pieces of defective address information comprising at least two pieces of defective address information having a same defective address; and

the second identification information of the at least two pieces of defective address information corresponds to different values, one of the at least two pieces of defective address information being enabled for use, and another of the at least two pieces of defective address information being prohibited from being used.

19 . The memory device of claim 1 , wherein:

the defective address information processing circuit further comprises a determining circuit configured to enable or disable the comparing sub-circuits based on first identification information of the initial target defective address information.

20 . The memory device of claim 1 , wherein:

the first defective address information memory comprises a first memory area, and a buffer circuit is configured to buffer the defective address information, corresponding to the initial target defective address information, from the first memory area and store the defective address information in the second defective address information memory.