IP Library Granted Patent US 12712152
Granted Patent B2
US 12712152 · App. 18/434,253 · Granted Aug 18, 2026

System and method for plasma processing

Inventors: Sergey Voronin (Albany, NY); Nicholas Smieszek (Albany, NY); Qi Wang (Albany, NY); Akiteru Ko (Albany, NY); Carl Smith (Albany, NY)
Assignee: Tokyo Electron Limited
H01J37/32174H01J37/32146H01J37/32706H10P50/242H01J2237/0044H01J2237/0473H01J2237/3341
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Quick Facts
Patent No.
US 12712152
App. No.
18/434,253
Granted
Aug 18, 2026
Kind
B2
Abstract

A method for plasma processing includes biasing a substrate by ramping a sheath voltage during a first phase of a plasma process and removing sidewall charge buildup on a feature of the substrate in an absence of substrate biasing during a second phase of the plasma process.

Claims (28)

1 . A method for plasma processing, the method comprising:

biasing a substrate by applying a bias voltage to a substrate holder or boundary electrode of a plasma processing chamber to ramp a sheath voltage during a first phase of a plasma process; and

exposing a feature to a plasma in an absence of substrate biasing during a second phase of the plasma process to remove sidewall charge buildup on the feature of the substrate, wherein the second phase of the plasma process comprises using a different process chemistry from the first phase of the plasma process.

2 . The method of claim 1 , wherein source power is higher during the second phase than during the first phase.

3 . The method of claim 1 , wherein source power is the same during the second phase as during the first phase.

4 . The method of claim 1 , wherein the sheath voltage is ramped with a slew rate in a range of 1 V/ms to 100 V/ms.

5 . The method of claim 1 , wherein the sheath voltage has a sinusoidal waveform while being ramped.

6 . The method of claim 1 , wherein the sheath voltage has a rectangular waveform while being ramped.

7 . The method of claim 1 , wherein the sheath voltage has a sawtooth waveform while being ramped.

8 . A method for plasma processing, the method comprising:

bombarding a feature of a substrate with ions from a first plasma generated with a first source power cycle from a power source, the ions being accelerated towards the substrate by ramping up a DC voltage provided to a boundary electrode above the substrate;

reducing the DC voltage provided to the boundary electrode to lower the acceleration of the ions towards the substrate; and

applying a second source power cycle from the power source to generate a second plasma and exposing the substrate to the second plasma to remove sidewall charge on a feature of the substrate, the second source power cycle having a greater power level than the first source power cycle.

9 . The method of claim 8 , wherein the DC voltage provided to the boundary electrode is a sinusoidal waveform with a frequency in a range of 0.01 Hz to 100 Hz.

10 . The method of claim 8 , wherein the first source power cycle is 80% or less of the maximum source power providable by the power source.

11 . The method of claim 8 , wherein the second source power cycle is greater than 80% of the maximum source power providable by the power source.

12 . The method of claim 8 , further comprising providing a bias voltage to the substrate while ramping the DC voltage provided to the boundary electrode.

13 . The method of claim 8 , wherein a duration of ramping the DC voltage provided to the boundary electrode is in a range of 0.1 ms to 100 s.

14 . A method for an etch process, the method comprising:

providing a substrate into a plasma processing chamber;

generating a plasma in the plasma processing chamber;

etching a feature of the substrate with energetic reactive ions by applying a bias voltage to a substrate holder or boundary electrode of the plasma processing chamber to produce an accelerating sheath voltage with a ramping amplitude, wherein the sheath voltage has a sinusoidal, rectangular, or sawtooth waveform; and

discharging the feature of the substrate with a source power cycle provided to the plasma processing chamber.

15 . The method of claim 14 , wherein the sheath voltage is reduced relative to the sheath voltage during the etching while discharging the feature of the substrate.

16 . The method of claim 14 , wherein providing the accelerating sheath voltage comprises providing a bias voltage to a substrate holder of the plasma processing chamber, the substrate being disposed on the substrate holder.

17 . The method of claim 14 , wherein providing the accelerating sheath voltage comprises providing a bias voltage to a boundary electrode of the plasma processing chamber, the boundary electrode being over the substrate.

18 . The method of claim 14 , wherein discharging the feature of the substrate is performed with a noble gas.

19 . The method of claim 14 , wherein the sheath voltage is ramped at a rate in a range of 0.01 V/ms to 1000 V/ms.