Advanced gate driver for improved EMI performance during MOSFET turn-on

1 . An adaptive gate driver for a power switch transistor in a switching power converter, comprising:

a gate drive circuit configured to charge a gate voltage of the power switch transistor through a variable gate drive resistance;

a first comparator configured to assert a first comparator output signal in response to the gate voltage being greater than a first threshold voltage;

a second comparator configured to assert a second comparator output signal in response to the gate voltage being greater than a second threshold voltage that is greater than the first threshold voltage; and

an adaptive drive control circuit configured to command the gate drive circuit to use a first gate drive resistance during a first portion of an on-time period for the power switch transistor while the first comparator output signal is not asserted and during a second portion of the on-time period for the power switch transistor following the assertion of the first comparator output signal and while the second comparator output signal is not asserted, and to use a second gate drive resistance during a third portion of the on-time period for the power switch transistor after the second comparator output signal is asserted and before a sampling period has expired, and to use a third gate drive resistance during a fourth portion of the on-time period for the power switch transistor after an expiration of the sampling period, wherein the adaptive drive control circuit is further configured to begin a timing of the sampling period in response to the assertion of the second comparator output signal, and wherein the adaptive drive control circuit is further configured to set the second gate drive resistance to be greater than the first gate drive resistance and to be greater than the third gate drive resistance in response to a detection that the switching power converter is in a discontinuous conduction mode of operation.

2 . The adaptive gate driver of claim 1 , wherein the adaptive drive control circuit is further configured to begin timing a startup delay at a beginning of the on-time period for the power switch transistor and to stop timing the startup delay in response to the assertion of the first comparator output signal.

3 . The adaptive gate driver of claim 2 , wherein the adaptive drive control circuit is further configured to compare a duration of the startup delay to a threshold delay and to increase the first gate drive resistance in response to the startup delay being less than the threshold delay.

4 . The adaptive gate driver of claim 3 , wherein the adaptive drive control circuit is further configured to decrease the first gate drive resistance in response to the startup delay being greater than the threshold delay.

5 . The adaptive gate driver of claim 1 , further comprising:

a sample-and-hold circuit configured to sample the gate voltage at an expiration of the sampling period to provide a sampled gate voltage.

6 . The adaptive gate driver of claim 5 , wherein the adaptive drive control circuit is further configured to adapt the second threshold voltage to equal a fraction of the sampled gate voltage.

7 . The adaptive gate driver of claim 6 , wherein the fraction is approximately three-fourths.

8 . The adaptive gate driver of claim 6 , wherein the adaptive drive control circuit is further configured to reduce the sampling period in response to a detection that the switching power converter is in a continuous conduction mode of operation.

9 . The adaptive gate driver of claim 1 , wherein the gate drive circuit comprises a plurality of transistors coupled between a gate of the power switch transistor and a power supply node, and wherein the adaptive drive control circuit comprises a logic circuit configured to command a first number of transistors in the plurality of transistors to switch on during the first portion of the on-time period for the power switch transistor and during the second portion of the on-time period for the power switch transistor and to command a second number of transistors in the plurality of transistors to switch on during the third portion of the on-time period for the power switch transistor.

10 . The adaptive gate driver of claim 9 , wherein the first number is greater than the second number.

11 . A method of adapting a gate drive resistance for a power switch transistor in a switching power converter, comprising:

charging a gate of the power switch transistor through a first gate drive resistance during a first portion of an on-time period for the power switch transistor while a gate voltage of the power switch transistor is less than a first threshold voltage and during a second portion of the on-time period for the power switch transistor while the gate voltage is less than a second threshold voltage that is greater than the first threshold voltage;

initiating a timing of a sampling period responsive to the gate voltage being greater than the second threshold voltage;

charging the gate through a second gate drive resistance during a third portion of the on-time period for the power switch transistor while the gate voltage is greater than the second threshold voltage and before an expiration of the sampling period, wherein the second gate drive resistance is greater than the first gate drive resistance;

sampling the gate voltage at an expiration of the sampling period to provide a sampled gate voltage;

charging the gate through a third gate drive resistance during a fourth portion of the on-time period for the power switch transistor following the expiration of the sampling period; and

adjusting the second threshold voltage to equal a fraction of the sampled gate voltage.

12 . The method of claim 11 , further comprising:

reducing the second gate drive resistance in response to a detection that the switching power converter is in a continuous conduction mode of operation.

13 . The method of claim 11 , further comprising:

increasing the first gate drive resistance in response to a duration of the first portion of the on-time period for the power switch transistor being less than a threshold delay; and

decreasing the first gate drive resistance in response to the duration of the first portion of the on-time period for the power switch transistor being greater than the threshold delay.

14 . The method of claim 11 , further comprising:

timing a maximum delay that begins with a beginning of the on-time period for the power switch transistor; and

transitioning from the third portion of the on-time period for the power switch transistor to the fourth portion of the on-time period for the power switch transistor in response to an expiration of the maximum delay.

15 . The method of claim 11 , wherein the third gate drive resistance is equal to the first gate drive resistance.

16 . A switching power converter, comprising:

an inductor;

a power switch transistor connected to the inductor; and

a gate drive control circuit configured to:

charge a gate of the power switch transistor through a first gate drive resistance during a first portion of an on-time period for the power switch transistor and during a second portion of the on-time period for the power switch transistor, wherein the first portion of the on-time period for the power switch transistor is terminated responsive to a gate voltage of the power switch transistor being greater than a first threshold voltage, and wherein the second portion of the on-time period for the power switch transistor is terminated responsive to the gate voltage of the power switch transistor being greater than a second threshold voltage that is greater than the first threshold voltage;

adapt the first gate drive resistance responsive to a duration of the first portion of the on-time period for the power switch transistor;

charge the gate through a second gate drive resistance during a third portion of the on-time period for the power switch transistor, wherein the second gate drive resistance is greater than the first gate drive resistance;

charge the gate through a third gate drive resistance during a fourth portion of the on-time period for the power switch transistor, wherein the second gate drive resistance is greater than the third gate drive resistance;

begin timing a sampling period in response to a beginning of the third portion of the on-time period for the power switch transistor;

transition from the third portion of the on-time period for the power switch transistor to the fourth portion of the on-time period for the power switch transistor in response to an expiration of the sampling period;

sample the gate voltage of the power switch transistor in response to the expiration of the sampling period to provide a sampled gate voltage; and

adapt the second threshold voltage to equal a fraction of the sampled gate voltage.

17 . The switching power converter of claim 16 , wherein a duration of the sampling period is approximately 300 ns.

18 . The switching power converter of claim 17 , wherein the switching power converter comprises a flyback converter.