Switching circuit
A switching circuit is provided. The switching circuit includes a first stage, a second stage, a decoupling inductor, a decoupling capacitor, and a semiconductor switch coupled between the first stage and the second stage. The first stage is configured to be coupled to a first bus. The second stage is configured to be coupled to a second bus. The decoupling inductor is coupled to the second stage, and the decoupling capacitor is coupled to the first stage. The semiconductor switch is configured to be controlled to convert a first current received at the first stage to a second current supplied to the second stage.
1 . A switching circuit, comprising:
a first stage configured to be coupled directly to a first line and a second line of a first bus;
a second stage configured to be coupled to a second bus;
a decoupling inductor coupled to said second stage;
a decoupling capacitor coupled across said first stage directly between the first line and the second line;
a semiconductor switch system comprising a first semiconductor switch and a second semiconductor switch coupled between said first stage and said second stage and configured to be controlled to convert a first current received at said first stage to a second current supplied to said second stage; and
a gate driver circuit system coupled to and configured to operate said semiconductor switch system, said gate driver circuit system comprising a first gate driver circuit coupled to said first semiconductor switch and a second gate driver circuit coupled to said second semiconductor switch,
wherein said switching circuit is configured to be coupled in parallel with a plurality of other switching circuits that each include an associated first semiconductor switch, an associated second semiconductor switch, and an associated decoupling capacitor, each decoupling capacitor configured to suppress transmission of parasitic currents to the other switching circuits,
wherein said first gate driver circuit is coupled to the associated first semiconductor switch of each of the plurality of other switching circuits and configured to provide a first control signal to the first semiconductor switch and the associated first semiconductor switch of each of the plurality of other switching circuits,
wherein said second gate driver circuit is coupled to the associated second semiconductor switch of each of the plurality of other switching circuits and configured to provide a second control signal to the second semiconductor switch and the associated second semiconductor switch of each of the plurality of other switching circuits, and
wherein said first gate driver circuit and said second gate driver circuit are controlled independently to (i) synchronize control of said first semiconductor switch and the associated first semiconductor switch of each of the plurality of other switching circuits using the first control signal, (ii) synchronize control of said second semiconductor switch and the associated second semiconductor switch of each of the plurality of other switching circuits using the second control signal, and (iii) provide substantially equal current sharing among said switching circuit and the plurality of other switching circuits.
2 . The switching circuit of claim 1 , wherein said first stage comprises a positive direct current (DC) line and a negative DC line, and wherein said decoupling capacitor is coupled across said positive DC line and said negative DC line.
3 . The switching circuit of claim 2 , wherein said first semiconductor switch is coupled between said positive DC line and said second stage at a midpoint node, and wherein said second semiconductor switch is coupled between said negative DC line and said second stage at the midpoint node, said second semiconductor switch configured to be controlled in coordination with said first semiconductor switch to convert the first current to the second current.
4 . The switching circuit of claim 3 , wherein said decoupling inductor is coupled in series between the midpoint node and said second stage.
5 . The switching circuit of claim 1 , wherein said decoupling capacitor comprises a capacitor having a capacitance in a range of 1/100 to 1/10 of a capacitance value of an energy storage capacitor for the switching circuit.
6 . The switching circuit of claim 1 , wherein said decoupling inductor comprises an inductor having an inductance in a range of 1/100 to 1/10 of an inductance value of a line filter inductor for the switching circuit.
7 . A paralleled switching circuit, comprising:
a first bus configured to supply a first current, the first bus comprising a first line and a second line;
a second bus configured to receive a second current;
a plurality of phase legs respectively coupled between said first bus and said second bus, each phase leg comprising a switching circuit configured to conduct a share of a total current supplied in the second current, each said switching circuit comprising:
a decoupling capacitor coupled directly to said first line and said second line of said first bus, the decoupling capacitor configured to suppresses transmission of parasitic currents from the associated switching circuit to the switching circuits of other phase legs of the plurality of phase legs;
a semiconductor switch system comprising a first semiconductor switch and a second semiconductor switch coupled between said first bus and said second bus, said semiconductor switch system configured to be controlled to convert the first current to the second current; and
a decoupling inductor coupled in series between said semiconductor switch and said second bus; and
a gate driver circuit system coupled to and configured to operate said semiconductor switch system of each switching circuit, said gate driver circuit system comprising a first gate driver circuit coupled to and configured to provide a first control signal to said first semiconductor switch of each switching circuit, said gate driver circuit further comprising a second gate driver circuit coupled to and configured to provide a second control signal to said second semiconductor switch of each switching circuit, wherein said first gate driver circuit and said second gate driver circuit are controlled independently to (i) synchronize control of said first semiconductor switch of each of the plurality of phase legs using the first control signal, (ii) synchronize control of said second semiconductor switch of each of the plurality of phase legs using the second control signal, and (iii) provide substantially equal current sharing among said semiconductor switch system of each of the plurality of phase legs switching circuits.
8 . The paralleled switching circuit of claim 7 , wherein said first bus comprises a positive direct current (DC) line and a negative DC line.
9 . The paralleled switching circuit of claim 8 further comprising an energy storage capacitor coupled between said positive DC line and said negative DC line.
10 . The paralleled switching circuit of claim 9 , wherein said energy storage capacitor comprises one or more capacitors having a combined capacitance in a range of 100 microfarad to 100 millifarad.
11 . The paralleled switching circuit of claim 8 , wherein said first semiconductor switch is coupled between said positive DC line and said decoupling inductor, and wherein said second semiconductor switch is coupled between said negative DC line and said decoupling inductor,
wherein said first gate driver circuit and said second gate driver circuit operate in a complementary manner to provide substantially equal current sharing among said plurality of phase legs.
12 . The paralleled switching circuit of claim 11 further comprising a digital signal processor (DSP) coupled to said first gate driver circuit and said second gate driver circuit, said DSP configured to control respective gate driver circuits for respective semiconductor switches in each switching circuit to convert the first current to the second current and provide the substantially equal current sharing among said plurality of phase legs.
13 . The paralleled switching circuit of claim 12 , wherein said DSP is further configured, in controlling the respective gate driver circuits, to conduct substantially equal respective shares of the total current through each of said switching circuits.
14 . The paralleled switching circuit of claim 12 , wherein said DSP is further configured, in controlling the respective gate driver circuits, to commutate the respective semiconductor switches at a switching frequency in a range of 1 KiloHertz to 1 MegaHertz.
15 . The paralleled switching circuit of claim 8 , wherein said second bus comprises a DC output bus.
16 . The paralleled switching circuit of claim 7 , wherein said second bus comprises an alternating current (AC) line.
17 . The paralleled switching circuit of claim 16 further comprising a line filter inductor coupled in series with said second bus.
18 . The paralleled switching circuit of claim 17 wherein said line filter inductor comprises an inductor having an inductance in a range of 1 to 100 microhenry.
19 . The paralleled switching circuit of claim 7 further comprising a current sensor coupled to said second bus and configured to detect an amplitude of the second current conducted over said second bus, and to provide a current measurement signal to a digital signal processor (DSP).