Power converter module
A power converter module includes power transistors and a substrate having a first surface and a second surface that opposes the first surface. A thermal pad is situated on the second surface of the substrate, and the thermal pad is configured to be thermally coupled to a heat sink. The power converter module also includes a control module mounted on a first surface of the substrate. The control module also includes control IC chips coupled to the power transistors. A first control IC chip controls a first switching level of the power converter module and a second control IC chip controls a second switching level of the power converter module. Shielding planes overlay the substrate. A first shielding plane is situated between the thermal pad and the first control IC chip and a second shielding plane is situated between the thermal pad and a second control IC chip.
1 . An apparatus, comprising:
a first shielding plane situated between a thermal pad and a first control IC chip and a second shielding plane situated between the thermal pad and a second control IC chip.
2 . The apparatus of claim 1 , wherein the first shielding plane and the second shielding plane overlay a substrate.
3 . The apparatus of claim 2 , further including a control module mounted on a first surface of the substrate.
4 . The apparatus of claim 3 , wherein the control module further includes an interconnect configured to provide a connection to a system bus.
5 . The apparatus of claim 4 , wherein the control module comprises a trace, and one of the first shielding plane and the second shielding plane underlies the trace.
6 . The apparatus of claim 5 , wherein the control module further comprises a wire bond coupled to the first control IC chip and coupled to the trace.
7 . The apparatus of claim 3 , wherein the control module further comprises a laminate substrate having a first surface and a second surface that opposes the first surface, wherein a patterned ground plane is situated on the first surface of the laminate substrate, and the first control IC chip and second control IC chip are mounted on the patterned ground plane.
8 . The apparatus of claim 7 , wherein the second surface of the laminate substrate overlies the first surface of the substrate.
9 . The apparatus of claim 8 , wherein the shielding planes are situated on the second surface of the laminate substrate.
10 . The apparatus of claim 8 , wherein the laminate substrate further comprises vias that couple the patterned ground plane to the shielding planes.
11 . The apparatus of claim 1 , wherein the first control IC chip controls a first switching level of the apparatus and the second control IC chip controls a second switching level of the apparatus.
12 . The apparatus of claim 1 , wherein the first control IC chip is coupled to a power transistor and the second control IC chip is coupled to another power transistor.
13 . The apparatus of claim 1 , wherein the apparatus is a power converter module.
14 . The apparatus of claim 1 , further comprising a patterned direct bonded copper (DBC) layer that is patterned to provide the first and second shielding planes.
15 . The apparatus of claim 14 , wherein an interconnect is mounted on the patterned DBC layer and the interconnect comprises pads for mounting the first and second control IC chips.
16 . The apparatus of claim 15 , wherein the interconnect comprises a trace, and one of the first shielding plane and the second shielding plane underlies the trace.
17 . The apparatus of claim 1 , wherein the first shielding plane and the second shielding plane block electromagnetic interference emanating through a heat sink.
18 . The apparatus of claim 12 , wherein the power transistors are gallium nitride (GaN) field effect transistors (FETs) or silicon carbide (SiC) FETs.
19 . The apparatus of claim 2 , wherein the substrate comprises a ceramic core.
20 . The apparatus of claim 1 , wherein the apparatus is a direct current (DC) to alternating current (AC) power converter module or a DC-to-DC power converter.
21 . The apparatus of claim 1 , wherein pins of the apparatus have a parasitic capacitance between about 0.02 picofarads (pF) and about 38 pF.