System and method for common mode voltage reduction for single phase 3 wire motor

1 . A method for reducing common mode voltage in a three-phase pulse width modulated (“PWM”) system that includes a controller and an inverter connected to a single phase 3 wire motor by a cable, the method comprising:

controlling, by the controller, operation of a plurality of switches of the inverter to generate three voltage signals provided to the motor over the cable that emulate a three-phase sinusoidal waveform using a sinusoidal PWM (“SPWM”) configuration;

phase shifting the three voltage signals by selecting a duty cycle overlap width;

identifying six sectors of the three-phase sinusoidal waveform based upon duty cycles of the three voltage signals;

identifying, for each of the six sectors, a Mid duty cycle and a Max duty cycle out of the three voltage signals;

determining, at a plurality of points for each of the six sectors, whether the identified Mid duty cycle is adjacent to the identified Max duty cycle; and

increasing, for each of the plurality of points, any Mid duty cycle that is adjacent to a corresponding Max duty cycle by the duty cycle overlap width;

wherein controlling operation of the plurality of switches includes modifying the SPWM configuration to reduce instances where a first set of switches of the plurality of switches coupled to a positive voltage are simultaneously ON or simultaneously OFF, or where a second set of switches of the plurality of switches coupled to a negative voltage are simultaneously ON or simultaneously OFF.

2 . The method of claim 1 , wherein modifying the SPWM configuration includes using one of a High Low High configuration or a Low High Low configuration for each of the six sectors.

3 . The method of claim 1 , wherein, for each of the six sectors, the identified Mid duty cycle is adjacent to the identified Max duty cycle when an absolute value of a sum of the Mid duty cycle and the Max duty cycle is less than the selected duty cycle overlap width plus one.

4 . The method of claim 1 , wherein identifying the six sectors includes identifying points where one of the three voltage signals crosses another of the three voltage signals.

5 . The method of claim 1 , wherein, for each of the six sectors, the Mid duty cycle is located between two of the three voltage signals.

6 . The method of claim 1 , wherein the selected duty cycle overlap width is related to a fundamental speed of the motor.

7 . The method of claim 1 , wherein the selected duty cycle overlap width is based upon a dead band set for the SPWM configuration and a phase relationship among the three voltage signals.

8 . The method of claim 1 , wherein selecting the duty cycle overlap width includes setting an initial duty cycle overlap width equal to a dead band duration of the SPWM configuration, then adjusting the initial duty cycle overlap width to identify a final duty cycle overlap width that reduces the common mode voltage.

9 . A system for reducing common mode voltage generated during operating of a single phase 3 wire motor, comprising:

a controller;

a memory device storing instructions;

an inverter controlled by the controller according to the instructions;

wherein execution of the instructions by the controller causes the controller to:

control operation of a plurality of switches of the inverter to generate three voltage signals provided to the motor that emulate a three-phase sinusoidal waveform using a sinusoidal PWM (“SPWM”) configuration;

phase shift the three voltage signals using a duty cycle overlap width;

identify six sectors of the three-phase sinusoidal waveform based upon duty cycles of the three voltage signals;

identify, for each of the six sectors, a Mid duty cycle and a Max duty cycle out of the three voltage signals;

determine, at a plurality of points for each of the six sectors, whether the identified Mid duty cycle is adjacent to the identified Max duty cycle;

increase, for each of the plurality of points, any Mid duty cycle that is adjacent to a corresponding Max duty cycle by the duty cycle overlap width; and

modify the SPWM configuration to reduce instances where a first set of switches of the plurality of switches coupled to a positive voltage are simultaneously ON or simultaneously OFF, or where a second set of switches of the plurality of switches coupled to a negative voltage are simultaneously ON or simultaneously OFF.

10 . The system of claim 9 , wherein the modified SPWM configuration includes using one of a High Low High configuration or a Low High Low configuration for each of the six sectors.

11 . The system of claim 9 , wherein, for each of the six sectors, the identified Mid duty cycle is adjacent to the identified Max duty cycle when an absolute value of a sum of the Mid duty cycle and the Max duty cycle is less than the duty cycle overlap width plus one.

12 . The system of claim 9 , wherein identifying the six sectors includes identifying points where one of the three voltage signals crosses another of the three voltage signals.

13 . The system of claim 9 , wherein, for each of the six sectors, the Mid duty cycle is located between two of the three voltage signals.

14 . The system of claim 9 , wherein the duty cycle overlap width is related to a fundamental speed of the motor.

15 . The system of claim 9 , wherein the duty cycle overlap width is based upon a dead band set for the SPWM configuration and a phase relationship among the three voltage signals.

16 . The system of claim 9 , wherein the duty cycle overlap width is determined by setting an initial duty cycle overlap width equal to a dead band duration of the SPWM configuration, then adjusting the initial duty cycle overlap width to identify a final duty cycle overlap width that reduces the common mode voltage.

17 . A non-transitory computer-readable medium with an executable program stored thereon for reducing common mode voltages in a three-phase pulse width modulated (“PWM”) system that includes an inverter connected to a single phase 3 wire motor, wherein the program instructs a controller to perform the following steps:

control operation of a plurality of switches of the inverter to generate three voltage signals provided to the motor that emulate a three-phase sinusoidal waveform using a sinusoidal PWM (“SPWM”) configuration;

phase shift the three voltage signals using a duty cycle overlap width;

identify six sectors of the three-phase sinusoidal waveform based upon duty cycles of the three voltage signals;

identify, for each of the six sectors, a Mid duty cycle and a Max duty cycle out of the three voltage signals;

determine, at a plurality of points for each of the six sectors, whether the identified Mid duty cycle is adjacent to the identified Max duty cycle;

increase, for each of the plurality of points, any Mid duty cycle that is adjacent to a corresponding Max duty cycle by the duty cycle overlap width; and

modify the SPWM configuration to reduce instances where a first set of switches of the plurality of switches coupled to a positive voltage are simultaneously ON or simultaneously OFF, or where a second set of switches of the plurality of switches coupled to a negative voltage are simultaneously ON or simultaneously OFF.

18 . The non-transitory computer-readable medium of claim 17 , wherein, for each of the six sectors, the identified Mid duty cycle is adjacent to the identified Max duty cycle when an absolute value of a sum of the Mid duty cycle and the Max duty cycle is less than the duty cycle overlap width plus one.

19 . The non-transitory computer-readable medium of claim 17 , wherein identifying the six sectors includes identifying points where one of the three voltage signals crosses another of the three voltage signals.

20 . The non-transitory computer-readable medium of claim 17 , wherein the duty cycle overlap width is related to a fundamental speed of the motor.