Constant transconductance-resistance tracking circuit for complementary metal oxide semiconductor amplifiers

1 . A constant transconductance-resistance (g m R) tracking biasing circuit comprising:

a first p-type metal oxide semiconductor (pMOS) transistor and a second pMOS transistor connected to form a first current mirror; and

a first n-type metal oxide semiconductor (nMOS) transistor and a second nMOS transistor connected to form a second current mirror, wherein gate electrodes of the first nMOS transistor and the second nMOS transistor are electrically connected together and wherein a drain electrode of the second nMOS transistor is directly connected to the gate electrode of the second nMOS transistor such that the second nMOS transistor is diode-connected,

the constant g m R tracking biasing circuit being configured to generate a bias output signal in accordance with currents flowing through the first pMOS transistor, the second pMOS transistor, the first nMOS transistor, and the second nMOS transistor, and

the bias output signal being configured to control a pMOS transconductance of an input pMOS transistor and an nMOS transconductance of an input nMOS transistor of an analog circuit, the input pMOS transistor and the input nMOS transistor being connected in series.

2 . The constant g m R tracking biasing circuit of claim 1 , comprising:

a pMOS tracking circuit portion comprising the first pMOS transistor and the second pMOS transistor; and

an nMOS tracking circuit portion comprising the first nMOS transistor and the second nMOS transistor,

wherein the bias output signal comprises:

an output pMOS bias voltage set by the pMOS tracking circuit portion based on a first current flowing through the first pMOS transistor and a second current flowing through the second pMOS transistor; and

an output nMOS bias voltage set by the nMOS tracking circuit portion based on a third current flowing through the first nMOS transistor and a fourth current flowing through the second nMOS transistor,

wherein the output pMOS bias voltage is configured to set a pMOS bias current and the output nMOS bias voltage is configured to set an nMOS bias current, and

wherein the pMOS transconductance of the input pMOS transistor and the nMOS transconductance of the nMOS input transistor are set based on a sum of the pMOS bias current and the nMOS bias current.

3 . The constant g m R tracking biasing circuit of claim 2 ,

wherein the pMOS tracking circuit portion further comprises:

a first amplifier circuit portion configured to control the first current flowing through the first pMOS transistor to be equal to the second current flowing through the second pMOS transistor, and

wherein the nMOS tracking circuit portion further comprises:

a second amplifier circuit portion configured to control the third current flowing through the first nMOS transistor to be equal to the fourth current flowing through the second nMOS transistor.

4 . The constant g m R tracking biasing circuit of claim 3 ,

wherein the pMOS tracking circuit portion further comprises:

a third nMOS transistor connected to a drain electrode of the first pMOS transistor; and

a fourth nMOS transistor connected to a drain electrode of the second pMOS transistor,

wherein the first amplifier circuit portion comprises a fifth nMOS transistor, the fifth nMOS transistor being diode-connected,

wherein the third nMOS transistor, the fourth nMOS transistor, and the fifth nMOS transistor have gate electrodes that are electrically connected together,

wherein the output pMOS bias voltage is set based on a voltage at the gate electrodes of the third nMOS transistor, the fourth nMOS transistor, and the fifth nMOS transistor,

wherein the nMOS tracking circuit portion further comprises:

a third pMOS transistor connected to a drain electrode of the first nMOS transistor; and

a fourth pMOS transistor connected to a drain electrode of the second nMOS transistor,

wherein the second amplifier circuit portion comprises a fifth pMOS transistor, the fifth pMOS transistor being diode-connected,

wherein the third pMOS transistor, the fourth pMOS transistor, and the fifth pMOS transistor have gate electrodes that are electrically connected together, and

wherein the output pMOS bias voltage is set based on a voltage at the gate electrodes of the third pMOS transistor, the fourth pMOS transistor, and the fifth pMOS transistor.

5 . The constant g m R tracking biasing circuit of claim 1 , wherein the bias output signal comprises an output bias voltage set based on:

a first current flowing through the first pMOS transistor and the first nMOS transistor; and

a second current flowing through the second pMOS transistor and the second nMOS transistor.

6 . The constant g m R tracking biasing circuit of claim 5 , further comprising an amplifier portion configured to control the first current flowing through the first pMOS transistor and the first nMOS transistor to be equal to the second current flowing through the second pMOS transistor and the second nMOS transistor.

7 . The constant g m R tracking biasing circuit of claim 6 ,

wherein the amplifier portion comprises:

a third nMOS transistor having a gate electrode connected to gate electrodes of the first nMOS transistor and the second nMOS transistor;

a fourth pMOS transistor having a source electrode connected to a source electrode of the third nMOS transistor and a gate electrode connected to a source electrode of the first pMOS transistor; and

a fifth nMOS transistor having a drain electrode connected to a source electrode of the fourth pMOS transistor, and

wherein the constant g m R tracking biasing circuit further comprises:

a sixth nMOS transistor having a drain electrode connected to a source electrode of the first pMOS transistor; and

a seventh nMOS transistor having a drain electrode connected to a source electrode of the second pMOS transistor and having a gate electrode connected to gate electrodes of the fifth nMOS transistor and the sixth nMOS transistor.

8 . The constant g m R tracking biasing circuit of claim 7 , wherein the output bias voltage is measured from:

the gate electrodes of the first nMOS transistor, the second nMOS transistor, and the third nMOS transistor, or

the gate electrodes of the fifth nMOS transistor, the sixth nMOS transistor, and the seventh nMOS transistor.

9 . The constant g m R tracking biasing circuit of claim 1 , wherein the bias output signal is configured to control an effective transconductance based on a sum of the pMOS transconductance of the input pMOS transistor and the nMOS transconductance of the nMOS input transistor to within ±1.5% of a nominal effective transconductance value over a temperature range of −40° C. to 125° C.

10 . An electrical circuit comprising:

a complementary metal oxide semiconductor (cMOS) analog amplifier comprising:

an input p-type metal oxide semiconductor (pMOS) transistor; and

an input n-type metal oxide semiconductor (nMOS) transistor; and

a constant transconductance-resistance (g m R) tracking biasing circuit comprising:

a first p-type metal oxide semiconductor (pMOS) transistor and a second pMOS transistor connected to form a first current mirror; and

a first n-type metal oxide semiconductor (nMOS) transistor and a second nMOS transistor connected to form a second current mirror, wherein gate electrodes of the first nMOS transistor and the second nMOS transistor are electrically connected together and wherein a drain electrode of the second nMOS transistor is directly connected to the gate electrode of the second nMOS transistor such that the second nMOS transistor is diode-connected,

the constant g m R tracking biasing circuit being configured to generate a bias output signal in accordance with currents flowing through the first pMOS transistor, the second pMOS transistor, the first nMOS transistor, and the second nMOS transistor, and

the bias output signal being configured to control a pMOS transconductance of the input pMOS transistor and an nMOS transconductance of the input nMOS transistor such that a gain of the analog amplifier, having an effective transconductance based on a sum of the pMOS transconductance and the nMOS transconductance, is substantially constant.

11 . The electrical circuit of claim 10 , further comprising:

a differential pair of pMOS transistors comprising the input pMOS transistor and a second input pMOS transistor; and

a differential pair of nMOS transistors comprising the input nMOS transistor and a second input nMOS transistor.

12 . The electrical circuit of claim 10 , wherein the constant g m R tracking biasing circuit comprises:

a pMOS tracking circuit portion comprising the first pMOS transistor and the second pMOS transistor configured to generate an output pMOS bias voltage; and

an nMOS tracking circuit portion comprising the first nMOS transistor and the second nMOS transistor configured to generate an output nMOS bias voltage,

wherein the output pMOS bias voltage is configured to set a pMOS bias current and the output nMOS bias voltage is configured to set an nMOS bias current, and

wherein the bias output signal is set based on a sum of the pMOS bias current and the nMOS bias current.

13 . The electrical circuit of claim 10 , wherein the bias output signal comprises an output bias voltage set based on:

a first current flowing through the first pMOS transistor and the first nMOS transistor; and

a second current flowing through the second pMOS transistor and the second nMOS transistor.

14 . The electrical circuit of claim 13 , wherein the constant g m R tracking biasing circuit comprises an amplifier portion configured to control the first current flowing through the first pMOS transistor and the first nMOS transistor to be equal to the second current flowing through the second pMOS transistor and the second nMOS transistor.

15 . A non-transitory computer-readable medium comprising a stored description of a constant transconductance-resistance (g m R) tracking biasing circuit, the constant g m R tracking biasing circuit comprising:

a first p-type metal oxide semiconductor (pMOS) transistor and a second pMOS transistor connected to form a first current mirror; and

a first n-type metal oxide semiconductor (nMOS) transistor and a second nMOS transistor connected to form a second current mirror, wherein gate electrodes of the first nMOS transistor and the second nMOS transistor are electrically connected together and wherein a drain electrode of the second nMOS transistor is directly connected to the gate electrode of the second nMOS transistor such that the second nMOS transistor is diode-connected,

the constant g m R tracking biasing circuit being configured to generate a bias output signal in accordance with currents flowing through the first pMOS transistor, the second pMOS transistor, the first nMOS transistor, and the second nMOS transistor, and

the bias output signal being configured to control a pMOS transconductance of an input pMOS transistor and an nMOS transconductance of an input nMOS transistor of an analog circuit, the input pMOS transistor and the input nMOS transistor being connected in series.

16 . The non-transitory computer-readable medium of claim 15 , wherein the stored description of the constant g m R tracking biasing circuit comprises descriptions of:

a pMOS tracking circuit portion comprising the first pMOS transistor and the second pMOS transistor; and

an nMOS tracking circuit portion comprising the first nMOS transistor and the second nMOS transistor,

wherein the bias output signal comprises:

an output pMOS bias voltage set by the pMOS tracking circuit portion based on a first current flowing through the first pMOS transistor and a second current flowing through the second pMOS transistor; and

an output nMOS bias voltage set by the nMOS tracking circuit portion based on on a third current flowing through the first nMOS transistor and a fourth current flowing through the second nMOS transistor,

wherein the output pMOS bias voltage is configured to set a pMOS bias current and the output nMOS bias voltage is configured to set an nMOS bias current, and

wherein the pMOS transconductance of the input pMOS transistor and the nMOS transconductance of the nMOS input transistor are set based on a sum of the pMOS bias current and the nMOS bias current.

17 . The non-transitory computer-readable medium of claim 16

wherein the description of the pMOS tracking circuit portion further comprises a description of:

a first amplifier circuit portion configured to control the first current flowing through the first pMOS transistor to be equal to the second current flowing through the second pMOS transistor, and

wherein the description of the nMOS tracking circuit portion further comprises a description of:

a second amplifier circuit portion configured to control the third current flowing through the first nMOS transistor to be equal to the fourth current flowing through the second nMOS transistor.

18 . The non-transitory computer-readable medium of claim 15 , wherein the bias output signal comprises an output bias voltage set based on:

a first current flowing through the first pMOS transistor and the first nMOS transistor; and

a second current flowing through the second pMOS transistor and the second nMOS transistor.

19 . The non-transitory computer-readable medium of claim 18 , wherein the description of the constant g m R biasing tracking circuit further comprises a description of an amplifier portion configured to control the first current flowing through the first pMOS transistor and the first nMOS transistor to be equal to the second current flowing through the second pMOS transistor and the second nMOS transistor.

20 . The non-transitory computer-readable medium of claim 19 ,

wherein the description of the amplifier portion further comprises descriptions of:

a third nMOS transistor having a gate electrode connected to gate electrodes of the first nMOS transistor and the second nMOS transistor;

a fourth pMOS transistor having a source electrode connected to a source electrode of the third nMOS transistor and a gate electrode connected to a source electrode of the first pMOS transistor; and

a fifth nMOS transistor having a drain electrode connected to a source electrode of the fourth pMOS transistor, and

wherein the description of the constant g m R biasing tracking circuit further comprises descriptions of:

a sixth nMOS transistor having a drain electrode connected to a source electrode of the first pMOS transistor; and

a seventh nMOS transistor having a drain electrode connected to a source electrode of the second pMOS transistor and having a gate electrode connected to gate electrodes of the fifth nMOS transistor and the sixth nMOS transistor.