IP Library › Granted Patent US 12712505

Granted Patent B2

US 12712505 · App. 17/977,840 · Granted Aug 18, 2026

Methods and apparatus to improve difference amplifiers

Inventors: Ankit Khanna (Tucson, AZ); Dimitar Trifonov (Vail, AZ); Partha S. Basu (Oro Valley, AZ); Sudheer Gangula (Tucson, AZ)

Assignee: TEXAS INSTRUMENTS INCORPORATED

H03F3/45475 H03F2203/45594

View Patent ↗

Loading inventors, assignments & file history…

Monitor This Case

Get email alerts when status or documents change.

Order Certified Copies

Most orders are placed with the USPTO same day — all within 24 business hours.

Order via The Patent Place →

Pre-filled with this patent's details

Quick Facts

Patent No.: US 12712505
App. No.: 17/977,840
Granted: Aug 18, 2026
Kind: B2

External Links

USPTO Patent Center↗ Full Patent PDF↗

Abstract

An example apparatus includes: a differential amplifier including: an inverting input coupled to a first input via a first resistor; a non-inverting input coupled to a second input via a second resistor; a first supply input coupled to the first input via a third resistor, and the first supply input coupled to the second input via a fourth resistor; a second supply input coupled to a current source; a non-inverting output; and an inverting output; a first transistor including a first control terminal and a first current terminal, the first control terminal coupled to the non-inverting output and the first current terminal coupled to the inverting input; and a second transistor including a second control terminal and a second current terminal, the second control terminal coupled to the inverting output and the second current terminal coupled to the non-inverting input.

Claims (112)

1 . An apparatus comprising:

a differential amplifier including:

an inverting input coupled to a first input via a first resistor;

a non-inverting input coupled to a second input via a second resistor;

a first supply input;

a second supply input coupled to a current source;

a non-inverting output; and

an inverting output;

a third resistor having a first terminal coupled to the first input and the first resistor;

a fourth resistor having a first terminal coupled to the second input and the second resistor and a second terminal coupled to the first supply input and a second terminal of the third resistor;

a first transistor including a first control terminal and a first current terminal, the first control terminal coupled to the non-inverting output and the first current terminal coupled to the inverting input; and

a second transistor including a second control terminal and a second current terminal, the second control terminal coupled to the inverting output and the second current terminal coupled to the non-inverting input.

2 . The apparatus of claim 1 , wherein the first transistor further includes a third current terminal and the second transistor further includes a fourth current terminal, and wherein the apparatus further comprises:

a third transistor including a third control terminal and a fifth current terminal, the third control terminal coupled to the second supply input, and the fifth current terminal coupled to the third current terminal; and

a fourth transistor including a fourth control terminal and a sixth current terminal, the fourth control terminal coupled to the second supply input, and the sixth current terminal coupled to the fourth current terminal.

3 . The apparatus of claim 1 , wherein the first transistor further includes a third current terminal and the second transistor further includes a fourth current terminal, and wherein the apparatus further comprises:

a charge pump;

a fifth resistor configured to be coupled between the third current terminal and the charge pump; and

a sixth resistor configured to be coupled between the fourth current terminal and the charge pump.

4 . The apparatus of claim 1 , further comprising a third transistor including a third current terminal and a fourth current terminal, the third current terminal coupled to the second supply input, and the fourth current terminal coupled to the current source.

5 . The apparatus of claim 1 , wherein the differential amplifier is a first differential amplifier, wherein the first transistor further includes a third current terminal, wherein the second transistor further includes a fourth current terminal, and wherein the apparatus further comprises a second differential amplifier configured to be coupled to the third current terminal and the fourth current terminal.

6 . A device comprising:

a first input;

a second input;

an input stage coupled to the first input and the second input, the input stage including:

a first transistor including a first control terminal, a first current terminal, and a second current terminal;

a second transistor including a second control terminal, a third current terminal, and a fourth current terminal;

a differential amplifier including:

a supply input coupled;

an inverting input coupled to the first current terminal;

a non-inverting input coupled to the third current terminal;

a first output coupled to the first control terminal; and

a second output coupled to the second control terminal;

a first resistor having a first terminal coupled to the supply input and a second terminal coupled to the first input;

a second resistor having a first terminal coupled to the supply input and the first terminal of the first resistor and a second terminal coupled to the second input;

a third resistor coupled between the inverting input and the first input; and

a fourth resistor coupled between the non-inverting input and the second input; and

a differential-to-single ended converter coupled to the second current terminal and the fourth current terminal.

7 . The device of claim 6 , wherein the supply input is a first supply input, the differential amplifier further including a second supply input, the input stage further comprising:

8 . The device of claim 6 , further comprising:

a charge pump;

a fifth resistor configured to be coupled between the second current terminal and the charge pump; and

a sixth resistor configured to be coupled between the fourth current terminal and the charge pump.

9 . The device of claim 6 , wherein the supply input is a first supply input, wherein the differential amplifier further includes a second supply input, and wherein the device further comprises a third transistor including a fifth current terminal and a sixth current terminal, the fifth current terminal coupled to the second supply input, and the sixth current terminal coupled to a current source.

10 . The device of claim 6 , wherein the differential amplifier is a first differential amplifier, the first transistor further includes a fifth current terminal, and the second transistor further includes a sixth current terminal, and wherein the device further comprises a second differential amplifier configured to be coupled to the fifth current terminal and the sixth current terminal.

11 . A difference amplifier having a first reference terminal operable to be coupled to a first terminal of a first resistor and having a second reference terminal operable to be coupled to a second terminal of the first resistor, the difference amplifier comprising:

an input stage coupled to the first reference terminal and the second reference terminal, the input stage including:

a floating differential amplifier coupled to the first reference terminal and the second reference terminal, the floating differential amplifier configured to convert a differential voltage across the first resistor to a differential output;

a first transistor coupled to the floating differential amplifier, the first transistor configured to be controlled by the differential output and pass a first current from the first reference terminal;

a second transistor coupled to the floating differential amplifier, the second transistor configured to be controlled by the differential output and pass a second current from the second reference terminal;

a second resistor configured to cause a first intermediate voltage by generating a first voltage drop based on the first current;

a third resistor configured to cause a second intermediate voltage by generating a second voltage drop based on the second current;

a fourth resistor coupled between the first reference terminal and a supply input of the floating differential amplifier; and

a fifth resistor coupled between the second reference terminal and the supply input of the floating differential amplifier; and

a differential amplifier configured to convert a differential voltage based on a difference between the first intermediate voltage and the second intermediate voltage to a single-ended voltage.

12 . The difference amplifier of claim 11 , further comprising:

a third transistor configured to pass current from the first transistor and enable a voltage difference between a first current terminal and a second current terminal, the first current terminal coupled to the first intermediate voltage; and

a fourth transistor configured to pass current from the second transistor and enable a voltage difference between a third current terminal and a fourth current terminal, the third current terminal coupled to the second intermediate voltage.

13 . The difference amplifier of claim 11 , further comprising a charge pump coupled to the second resistor and the third resistor, the charge pump configured to increase a common-mode range of the floating differential amplifier.

14 . The difference amplifier of claim 13 , further comprising a current source coupled to the floating differential amplifier by a third transistor.

15 . The difference amplifier of claim 11 , wherein the floating differential amplifier further comprises:

a substrate layer;

an N-type buried layer configured to be coupled to the first reference terminal by a fourth resistor; and

a buried oxide layer coupled between the substrate layer and the N-type buried layer.

16 . The difference amplifier of claim 15 , wherein the N-type buried layer is configured to be coupled to the first reference terminal by the fourth resistor and coupled to the second reference terminal by a fifth resistor.

17 . The difference amplifier of claim 11 , wherein the fourth and fifth resistors are configured to set the supply input using a common-mode voltage of the first and second reference terminals.

18 . An apparatus comprising:

a differential amplifier including:

an inverting input coupled to a first input via a first resistor;

a non-inverting input coupled to a second input via a second resistor;

a first supply input coupled to the first input via a third resistor, and the first supply input coupled to the second input via a fourth resistor;

a second supply input coupled to a current source;

a non-inverting output;

an inverting output;

a substrate layer;

an N-type buried layer coupled to the first supply input; and

a buried oxide layer coupled between the substrate layer and the N-type buried layer;

19 . The apparatus of claim 18 , wherein the first transistor further includes a third current terminal and the second transistor further includes a fourth current terminal, further comprising:

20 . The apparatus of claim 18 , wherein the first transistor further includes a third current terminal and the second transistor further includes a fourth current terminal, further comprising:

a charge pump;

a fifth resistor configured to be coupled between the third current terminal and the charge pump; and

a sixth resistor configured to be coupled between the fourth current terminal and the charge pump.

21 . The apparatus of claim 18 , further comprising a third transistor including a third current terminal and a fourth current terminal, the third current terminal coupled to the second supply input, and the fourth current terminal coupled to the current source.

22 . The apparatus of claim 18 , wherein the N-type buried layer is configured to be coupled to the first input by the third resistor and coupled to the second input by the fourth resistor.

23 . The apparatus of claim 18 , wherein the differential amplifier is a first differential amplifier, the first transistor further includes a third current terminal, and the second transistor further includes a fourth current terminal, further comprising a second differential amplifier configured to be coupled to the third current terminal and the fourth current terminal.

24 . A device comprising:

a first input;

a second input;

an input stage coupled to the first input and the second input, the input stage including:

a first transistor including a first control terminal, a first current terminal, and a second current terminal;

a second transistor including a second control terminal, a third current terminal, and a fourth current terminal;

a differential amplifier including:

a supply input coupled;

an inverting input coupled to the first current terminal;

a non-inverting input coupled to the third current terminal;

a first output coupled to the first control terminal;

a second output coupled to the second control terminal;

a substrate layer;

an N-type buried layer coupled to the supply input; and

a buried oxide layer coupled between the substrate layer and the N-type buried layer;

a first resistor coupled between the supply input and the first input;

a second resistor coupled between the supply input and the second input;

a third resistor coupled between the inverting input and the first input; and

a fourth resistor coupled between the non-inverting input and the second input; and

a differential-to-single ended converter coupled to the second current terminal and the fourth current terminal.

25 . The device of claim 24 , wherein the N-type buried layer is configured to be coupled to the first input by the first resistor and coupled to the second input by the second resistor.