Accurate delay generator and accurate oscillator
View Patent ↗A delay circuit comprising self calibrating means. The process, supply and temperature dependent error of intrinsic delay of a comparator in a delay circuit is self calibrated out of the generated delay. The intrinsic delay is used to self adjust the delay generating reference to remove effect of the intrinsic delay during delay generation. A relaxation oscillator circuit comprising the delay circuit blocks to create a process, supply and temperature independent oscillation frequency.
1 . A method for calibrating a delay generation circuit comprising:
comparator based delay generator including:
a comparator to generate a delayed output signal
wherein said comparator responds to an input after an intrinsic delay TPD which is a process, supply and temperature dependent parameter; and
a first signal ramp produced at a controlled slope to create a predetermined time varying signal, to generate the desired delay, coupled to said comparator first input; and
a predetermined reference signal coupled to said comparator first input; and
a switch to select said reference, in the calibration phase, or said first signal ramp, in the delay phase, to be coupled to said comparator first input; and
a second signal ramp, produced at a negative slope of said first signal ramp, coupled to said comparator second input; and
a signal hold means to hold the signal level of said second signal ramp
wherein after calibration said hold signal level is substantially in accordance with the following relationship to said reference, said comparator propagation delay TPD, and said first signal ramp slope S:
HOLD_SIGNAL
=
REFERENCE
-
T
PD
S
a logic circuit to generate the control signals.
2 . The circuit according to claim 1 , wherein during said calibration phase said reference is coupled to said comparator first input and said second signal ramp, starting from a value greater than said reference, is coupled to said comparator second input.
3 . The circuit according to claim 2 , wherein during said calibration phase said second signal ramp level, at the time instant said comparator changes its state, is maintained by said signal hold means, This will also indicate the end of said calibration phase.
4 . The circuit according to claim 3 , wherein during said delay phase said hold signal is coupled to said comparator second input and said first signal ramp is coupled to said comparator first input.
5 . The circuit according to claim 4 , wherein during said delay phase said first signal ramp is activated by an input signal event and said comparator changes its state when said first signal ramp comparison with said hold signal satisfies the comparison condition.
6 . The circuit according to claim 5 , wherein the delay generated from the input signal event time T START to said comparator state change time T SC is substantially in accordance with the following relationship:
DELAY
=
∫
T
s
t
a
r
t
T
s
c
REFERENCE
-
RAMP_START
S
d
t
wherein RAMP_START is the signal level of the first signal ramp at the initiation of said delay phase
whereby eliminating said process, supply, temperature dependent comparator propagation delay T PD .
7 . The circuit according to claim 1 , wherein said first signal ramp and said second signal ramp in one embodiment are achieved by means of a predetermined current source and a capacitor.
8 . The circuit according to claim 1 , wherein the means to hold said second signal ramp level is achieved by means of a capacitor.
9 . An accurate relaxation oscillator circuit comprising:
two comparator based delay circuits each including:
a comparator to generate a delayed output signal
wherein said comparator responds to an input after an intrinsic delay T PD which is a process, supply and temperature dependent parameter;
a first signal ramp produced at a controlled slope to create a predetermined time varying signal, to generate a portion of the oscillation time period, coupled to said comparator first input; and
a predetermined reference signal coupled to said comparator first input; and
a switch to select said reference, in the calibration phase, or said first signal ramp, in the delay phase, to be coupled to said comparator first input; and
a second signal ramp, produced at a negative slope of said first signal ramp, coupled to said comparator second input; and
a signal hold means to hold the signal level of said second signal ramp
wherein after calibration said hold signal level is substantially in accordance with the following relationship to said reference, said comparator propagation delay T PD and said first signal ramp slope S:
HOLD_SIGNAL
=
REFERENCE
-
T
PD
S
a logic circuit that takes the output of said two delay circuits and generates the right logic signals for controlling the timing and calibration of each of the delay circuits.
10 . The circuit according to claim 9 , wherein said calibration phase of each said delay circuit is followed by said delay phase of that respective circuit.
11 . The circuit according to claim 10 , wherein the output of said first delay circuit is used as an activation signal for said first signal ramp of said second delay circuit.
12 . The circuit according to claim 11 , wherein the output of said second delay circuit is used as an activation signal for said first signal ramp of said first delay circuit.
13 . The circuit according to claim 12 , wherein said oscillator circuit sustains continuous alternate delay phases of said two delay circuits to generate a oscillation frequency substantially in accordance with the following relationship:
FREQUENCY
=
1
D
E
L
A
Y
1
+
DELAY
2
wherein DELAY 1 and DELAY 2 are the delays generated by said two delay circuits respectively in their said delays phases
whereby eliminating the dependence of the frequency on said process, supply, temperature dependent comparator propagation delay T PD .