Communication circuit with analog duty-cycle detection

1 . A circuit comprising:

an analog duty-cycle detector circuit including:

off-time detection circuitry having a first terminal, a second terminal, a third terminal, and a fourth terminal, the off-time detection circuitry including a first transistor and a first capacitor, the first transistor having a first terminal, a second terminal, and a control terminal, the first capacitor having a first terminal and a second terminal, the first terminal of the first transistor coupled to the first terminal of the off-time detection circuitry, the second terminal of the first transistor coupled to the first terminal of the first capacitor;

on-time detection circuitry having a first terminal, a second terminal, a third terminal, and a fourth terminal, the on-time detection circuitry including a second transistor and a second capacitor, the second transistor having a first terminal, a second terminal, and a control terminal, the second capacitor having a first terminal and a second terminal, the first terminal of the second transistor coupled to the first terminal of the on-time detection circuitry, the second terminal of the second transistor coupled to the first terminal of the second capacitor;

compare circuitry having a first terminal, a second terminal, and a third terminal, the first terminal of the compare circuitry coupled to the third terminal of the off-time detection circuitry, and the second terminal of the compare circuitry coupled to the third terminal of the on-time detection circuitry, the compare circuitry configured to compare a charge across the first capacitor and a charge across the second capacitor; and

a controller having a reset control terminal, the reset control terminal coupled to the fourth terminal of the off-time detection circuitry and to the fourth terminal of the on-time detection circuitry.

2 . The circuit of claim 1 , wherein the analog duty-cycle detector circuit includes a latch circuit having a first terminal, a second terminal, and a third terminal, the controller has a sample control terminal, the first terminal of the latch circuit coupled to the third terminal of the compare circuitry, the second terminal of the latch circuit coupled to the sample control terminal.

3 . The circuit of claim 1 , wherein the analog duty-cycle detector circuit includes current source circuitry having an output coupled to the first terminal of the off-time detection circuitry and to the first terminal of the on-time detection circuitry, the off-time detection circuitry includes a third transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the third transistor coupled to the first terminal of the first capacitor, the second terminal of the third transistor coupled to a threshold voltage source, the control terminal of the third transistor coupled to the fourth terminal of the off-time detection circuitry, the on-time detection circuitry including a fourth transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the fourth transistor coupled to the first terminal of the second capacitor, the second terminal of the fourth transistor coupled to the threshold voltage source, and the control terminal of the fourth transistor coupled to the fourth terminal of the on-time detection circuitry.

4 . The circuit of claim 3 , wherein the controller is configured to:

provide a first control signal to the control terminal of the first transistor;

provide a second control signal to the control terminal of the second transistor;

provide a third control signal to the control terminal of the third transistor; and

provide a fourth control signal to the control terminal of the fourth transistor, the first and third control signals following a first control sequence having a first interval and a second interval responsive to a reset trigger for the off-time detection circuitry, the first and third transistors turned on together during the first interval of the first control sequence, the first transistor turned off and the third transistor turned on during the second interval of the first control sequence, the second and fourth control signals following a second control sequence having a first interval and a second interval responsive to a reset trigger for the on-time detection circuitry, the second and fourth transistors turned on together during the first interval of the second control sequence, the second transistor turned off and the fourth transistor turned on during the second interval of the second control sequence.

5 . The circuit of claim 3 , wherein the controller is configured to:

provide a first control signal to the control terminal of the first transistor; and

provide a second control signal to the control terminal of the second transistor, the first and second control signals following a first control sequence having a first interval and a second interval responsive to a transition from off-time detection to on-time detection, the first and second transistors turned off during the first interval of the first control sequence, the first transistor turned off and the second transistor turned on during the second interval of the first control sequence, the first and second control signals following a second control sequence having a first interval and a second interval responsive to a transition from on-time detection to off-time detection, the first and second transistors turned off during the first interval of the second control sequence, the first transistor turned on and the second transistor turned off during the second interval of the second control sequence.

6 . The circuit of claim 1 , wherein the analog duty-cycle detector circuit includes current source circuitry having a first output and a second output, the first output coupled to the first terminal of the off-time detection circuitry, and the second output coupled to the first terminal of the on-time detection circuitry, the off-time detection circuitry includes a third transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the third transistor coupled to the first terminal of the first capacitor, the second terminal of the third transistor coupled to a ground terminal, the control terminal of the third transistor coupled to the fourth terminal of the off-time detection circuitry, the on-time detection circuitry includes a fourth transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the fourth transistor coupled to the first terminal of the second capacitor, the second terminal of the fourth transistor coupled to the ground terminal, and the control terminal of the fourth transistor coupled to the fourth terminal of the on-time detection circuitry.

7 . The circuit of claim 1 , wherein the controller is a first controller, the off-time detection circuitry is first off-time detection circuitry, the on-time detection circuitry is first on-time detection circuitry, the compare circuitry is first compare circuitry, the analog duty-cycle detector circuit includes a first duty-cycle detector circuit and a second duty-cycle detector circuit, the first duty-cycle detector circuit including the first off-time detection circuitry, the first on-time detection circuitry, and the first compare circuitry, the second duty-cycle detector circuit including a second controller, second off-time detection circuitry, second on-time detection circuitry, and second compare circuitry, the analog duty-cycle detector circuit including combine circuitry to provide combined duty-cycle detection results responsive to first duty-cycle detection results obtained by the first duty-cycle detector circuit and second duty-cycle detection results obtained by the second duty-cycle detector circuit.

8 . The circuit of claim 7 , wherein the combine circuitry is configured to:

receive first duty-cycle detection results;

receive second duty-cycle detection results;

update the first duty-cycle detection results to equal to the second duty-cycle detection results responsive to a first delayed sample control signal;

update the second duty-cycle detection results to equal to the first duty-cycle detection results responsive to a second delayed sample control signal; and

provide the combined duty-cycle detection results responsive to the duty-cycle detection results, the second duty-cycle detection results, the updated first duty-cycle detection results, and the updated second duty-cycle detection results.