Circuit pre-charging

1 . A circuit, comprising:

a first transistor having a control terminal and first and second terminals;

a first diode having an anode and a cathode, the anode of the first diode coupled to the second terminal of the first transistor;

a second diode having an anode and a cathode, the anode of the second diode coupled to the cathode of the first diode;

a second transistor having a control terminal and first and second terminals, the first terminal of the second transistor coupled to the cathode of the second diode;

a third diode having an anode and a cathode, the anode of the third diode coupled to the second terminal of the first transistor;

a first switch having first and second terminals, the first terminal of the first switch coupled to the cathode of the third diode;

a fourth diode having an anode and a cathode, the cathode of the fourth diode coupled to the first terminal of the second transistor;

a second switch having first and second terminals, the first terminal of the second switch coupled to the anode of the fourth diode;

a third switch having first and second terminals, the first terminal of the third switch coupled to the second terminal of the first transistor;

a fourth switch having first and second terminals, the first terminal of the fourth switch coupled to the second terminal of the third switch, and the second terminal of the fourth switch coupled to a ground terminal;

a fifth switch having first and second terminals, the first terminal of the fifth switch coupled to the first terminal of the second transistor; and

a sixth switch having first and second terminals, the first terminal of the sixth switch coupled to the second terminal of the fifth switch, and the second terminal of the sixth switch coupled to the ground terminal,

wherein the circuit is configured to receive control signals and, in response to the control signals:

in a first operational state, open the first through sixth switches responsive to the first or second transistors being conductive;

in a second operational state, close the third through sixth switches and open the first and second switches, while the first and second transistors are non-conductive; and

in a third operational state, close first and second switches and open the third through sixth switches, while the first and second transistors are non-conductive.

2 . The circuit of claim 1 , wherein the first terminal of the first transistor is coupled to a first voltage supply terminal, the second terminal of the second transistor is coupled to a second voltage supply terminal, and the circuit is configured to receive a first voltage at the first voltage supply terminal and a second voltage at the second voltage supply terminal, the first voltage opposite in polarity to the second voltage supply terminal.

3 . The circuit of claim 2 , wherein the second terminal of the first switch is coupled to a third voltage supply terminal, the second terminal of the second switch is coupled to a fourth voltage supply terminal, and the circuit is configured to receive a third voltage at the third voltage supply terminal and a fourth voltage at the fourth voltage supply terminal, the third voltage opposite in polarity to the first voltage, and the fourth voltage is opposite in polarity to the second voltage supply terminal.

4 . The circuit of claim 1 , further comprising a linear amplifier having an output coupled to the cathode of the first diode.

5 . The circuit of claim 1 , further comprising a receiver circuit having an input coupled to the cathode of the first diode.

6 . The circuit of claim 5 , further comprising a seventh switch coupled between the input of the receiver circuit and the cathode of the first diode.

7 . The circuit of claim 1 , further comprising a transducer coupled to the cathode of the first diode.

8 . A circuit, comprising:

a first transistor having a control terminal and first and second terminals;

a first diode having an anode and a cathode, the anode of the first diode coupled to the second terminal of the first transistor;

a second diode having an anode and a cathode, the anode of the second diode coupled to the cathode of the first diode;

a second transistor having a control terminal and first and second terminals, the first terminal of the second transistor coupled to the cathode of the second diode;

a first switch having first and second terminals, the first terminal of the first switch coupled to the second terminal of the first transistor;

a second switch having first and second terminals, the first terminal of the second switch coupled to the second terminal of the first switch;

a third switch having first and second terminals, the first terminal of the third switch coupled to a ground terminal, and the second terminal of the third switch coupled to the second terminal of the second switch; and

a fourth switch having first and second terminals, the first terminal of the fourth switch coupled to the second terminal of the second switch.

9 . The circuit of claim 8 , further comprising:

a fifth switch having first and second terminals, the first terminal of the fifth switch coupled to the first terminal of the second transistor;

a sixth switch having first and second terminals, the first terminal of the sixth switch coupled to the second terminal of the fifth switch;

a seventh switch having first and second terminals, and the second terminal of the seventh switch coupled to the second terminal of the sixth switch; and

an eighth switch having first and second terminals, the first terminal of the eighth switch coupled to the second terminal of the sixth switch, and the second terminal of the eighth switch coupled to the ground terminal.

10 . The circuit of claim 9 , wherein the first switch and the second switch are each implemented as transistors having bulk diodes, each having an anode and a cathode, and wherein the first switch and the second switch are arranged such that the anodes of the bulk diodes are coupled together or the cathodes of the bulk diodes are coupled together.

11 . The circuit of claim 9 , wherein the first, second, fifth, and sixth switches have a higher voltage tolerance than the third, fourth, seventh, and eighth switches.

12 . The circuit of claim 9 , wherein the circuit is configured to receive control signals and, in response to the control signals:

in a first operational state, close the first, fourth, fifth, and seventh switches, and open the second, third, sixth, and eighth switches, while the first and second transistors are non-conductive;

in a second operational state, open the first through eighth switches while the first or second transistors are conductive;

in a third operational state, close the first through third, fifth, sixth, and eighth switches and open the fourth and seventh switches, while the first and second transistors are non-conductive; and

in a fourth operational state, close the first, second, and fourth through seventh switches and open the third and eighth switches, while the first and second transistors are non-conductive.

13 . The circuit of claim 12 , wherein the first operational state is a linear amplifier transmission state, the second operational state is a pulser transmission state, the third operational state is a clearing state, and the fourth operational state is a pre-charging state.

14 . The circuit of claim 13 , wherein a receive mode of the circuit begins with the third operational state, following the fourth operational state ending a transmit mode of the circuit.

15 . The circuit of claim 8 , further comprising a linear amplifier having an output coupled to the cathode of the first diode.

16 . The circuit of claim 8 , further comprising a receiver circuit having an input coupled to the cathode of the first diode.

17 . The circuit of claim 16 , further comprising a fifth switch coupled between the input of the receiver circuit and the cathode of the first diode.

18 . The circuit of claim 8 , further comprising a transducer coupled to the cathode of the first diode.