Single-to-differential circuit and method for operating the same

1 . An integrated circuit, comprising:

an input stage, configured to receive an input clock signal, and convert the input clock signal into a first signal and a second signal;

a first output stage, comprising: a first inverter and a first buffer circuit coupled to a first output terminal of the integrated circuit, wherein the first inverter and the first buffer circuit receive the second signal and the first signal, respectively, and generate a first output clock signal at the first output terminal; and

a second output stage, comprising a second inverter and a second buffer circuit coupled to a second output terminal of the integrated circuit, wherein the second inverter and the second buffer circuit receive the first signal and the second signal, respectively, and generate a second output clock signal at the second output terminal,

wherein the first output clock signal and the second output clock signal are differential clock signals,

wherein the input stage comprises:

a third inverter, configured to convert the input clock signal to generate a third signal at a first node;

a fourth inverter, configured to convert the input clock signal to generate the second signal at a second node;

a fifth inverter, configured to convert the third signal to generate the first signal at a third node;

a third buffer circuit, coupled between the input clock signal and the first node; and

a fourth buffer circuit, coupled between the first node and the second node.

2 . The integrated circuit of claim 1 , wherein the first output clock signal and the second output clock signal are an in-phase clock signal and an out-phase clock signal with respect to the input clock signal.

3 . The integrated circuit of claim 1 , wherein the first output clock signal substantially aligns with the second output clock signal.

4 . The integrated circuit of claim 1 , wherein the first buffer circuit and the second buffer circuit are configured to increase driving capabilities of the first inverter and the second inverter, respectively.

5 . The integrated circuit of claim 4 , wherein the first buffer circuit and the second buffer circuit comprise logic buffers.

6 . The integrated circuit of claim 5 , wherein a layout of each of the first buffer circuit and the second buffer circuit is symmetric to that of each of the first inverter and the second inverter.

7 . The integrated circuit of claim 6 , wherein each of the first inverter and the second inverter comprises:

a first P-type transistor, comprising a gate terminal receiving a first input signal, a drain terminal connected to a third output terminal, and a source terminal connected to a power supply voltage; and

a first N-type transistor, comprising a gate terminal receiving the first input signal, a drain terminal connected to the third output terminal, and a source terminal connected to a reference voltage.

8 . The integrated circuit of claim 7 , wherein each logic buffer comprises:

a second P-type transistor, comprising a gate terminal receiving a second input signal, a drain terminal connected to the reference voltage, and a source terminal connected to a fourth output terminal; and

a second N-type transistor, comprising a gate terminal receiving the second input signal, a drain terminal connected to the power supply voltage, and a source terminal connected to the fourth output terminal.

9 . The integrated circuit of claim 1 , further comprising: a latch coupled between the second node and the third node.

10 . An integrated circuit, comprising:

a first inverter stage, configured to convert an input clock signal into a first signal;

a second inverter stage, configured to convert the input clock signal to a second signal;

a first output stage, comprising: a first inverter and a first buffer circuit coupled to a first output terminal, wherein the first inverter and the first buffer circuit receive the second signal and the first signal, respectively, and generate a first output clock signal at the first output terminal; and

a second output stage, comprising a second inverter and a second buffer circuit coupled to a second output terminal, wherein the second inverter and the second buffer circuit receive the first signal and the second signal, respectively, and generate a second output clock signal at the second output terminal,

wherein the first output clock signal and the second output clock signal constitute a differential clock signal,

wherein the first inverter stage comprises a third inverter and a fourth inverter connected in series through a first node, and the fourth inverter is connected to the second inverter at a second node,

wherein the second inverter stage comprises a fifth inverter, which is connected to the first inverter at a third node.

11 . The integrated circuit of claim 10 , wherein the first output clock signal and the second output clock signal are an in-phase clock signal and an out-phase clock signal with respect to the input clock signal.

12 . The integrated circuit of claim 10 , wherein the first buffer circuit and the second buffer circuit comprise logic buffers.

13 . The integrated circuit of claim 12 , wherein a layout of each of the first buffer circuit and the second buffer circuit is symmetric to that of each of the first inverter and the second inverter.

14 . The integrated circuit of claim 10 , further comprising:

a third buffer circuit, coupled between the input clock signal and the second node; and

a fourth buffer circuit, coupled between the first node and the third node.

15 . The integrated circuit of claim 10 , wherein the first output clock signal substantially aligns with the second output clock signal.

16 . The integrated circuit of claim 10 , wherein the first buffer circuit and the second buffer circuit are configured to increase driving capabilities of the first inverter and the second inverter, respectively.

17 . A method, comprising:

utilizing a first conversion circuit to convert an input clock signal to a first signal;

utilizing a second conversion circuit to convert the input clock signal to a second signal;

utilizing a first inverter to operate in conjunction with a first buffer circuit to generate a first output clock signal using the second signal and the first signal, respectively; and

utilizing a second inverter to operate in conjunction with a second buffer circuit to generate a second output clock signal using the first signal and the second signal, respectively,

wherein the first output clock signal and the second output clock signal are differential clock signals,

wherein the first conversion circuit comprises a third inverter and a fourth inverter connected in series through a first node, and the fourth inverter is connected to the second inverter at a second node,

wherein the second conversion unit comprises a fifth inverter, which is connected to the first inverter at a third node.

18 . The method of claim 17 , wherein the first buffer circuit and the second buffer circuit comprise logic buffers.

19 . The method of claim 17 , wherein the first output clock signal substantially aligns with the second output clock signal.

20 . The method of claim 17 , wherein the first buffer circuit and the second buffer circuit are configured to increase driving capabilities of the first inverter and the second inverter, respectively.