Level shifter and memory device including the same
A level shifter includes a first circuit that pulls down a first output node and a first intermediate node based on an input signal, and pulls down a second output node and a second intermediate node based on an inverted input signal of the input signal, and a second circuit that pulls up the second output node based on the first intermediate node when the first circuit pulls down the first output node to a supply voltage, and pulls up the first output node based on the second intermediate node to the supply voltage when the first circuit pulls down the second output node.
1 . A level shifter comprising:
a first circuit configured to pull down a first output node and a first intermediate node based on an input signal, and pull down a second output node and a second intermediate node based on an inverted input signal of the input signal; and
a second circuit configured to pull up the second output node to a supply voltage based on the first intermediate node when the first circuit pulls down the first output node, and pull up the first output node to the supply voltage based on the second intermediate node when the first circuit pulls down the second output node,
wherein the second circuit comprises:
a first transistor comprising a drain terminal connected to a first node, a source terminal connected to the second intermediate node, and a gate configured to receive a first bias signal,
a second transistor comprising a drain terminal connected to a line configured to apply the supply voltage, a source terminal connected to the first output node, and a gate connected to the first node,
a third transistor comprising a drain terminal connected to the first intermediate node, a source terminal connected to a second node, and a gate configured to receive the first bias signal, and
a fourth transistor comprising a drain terminal connected to the line configured to apply the supply voltage, a source terminal connected to the second output node, and a gate connected to the second node.
2 . The level shifter of claim 1 , wherein the first circuit comprises:
a fifth transistor connected between a line that applies a ground voltage and a third node, and includes a gate configured to receive the input signal; and
a sixth transistor connected between the line that applies the ground voltage and a fourth node, and includes a gate configured to receive the inverted input signal.
3 . The level shifter of claim 2 , further comprising:
a third circuit configured to adjust upper limits of voltage levels of the first intermediate node and the second intermediate node to be equal to or lower than a first bias voltage, and adjust lower limits of voltage levels of the first output node and the second output node to be equal to or higher than a second bias voltage different from the first bias voltage.
4 . The level shifter of claim 3 , wherein the first bias voltage is lower than the supply voltage, and the second bias voltage is higher than the ground voltage.
5 . The level shifter of claim 3 , wherein the third circuit comprises:
a seventh transistor connected between the first intermediate node and the first third node, and includes a gate that is configured to receive the first bias voltage;
an eighth transistor connected between the second intermediate node and the fourth node, and includes a gate configured to receive the first bias voltage;
a ninth transistor connected between the first output node and the first intermediate node, and includes a gate configured to receive the second bias voltage; and
a tenth transistor connected between the second output node and the second intermediate node, and includes a gate configured to receive the second bias voltage.
6 . The level shifter of claim 1 , further comprising:
a third circuit configured to pull up an output node configured to output an output signal, to the supply voltage, based on the voltage level of the first output node, and pull down the output node based on the inverted input signal.
7 . The level shifter of claim 6 , wherein the third circuit comprises:
a fifth transistor connected between a line that applies the supply voltage and a third node, and includes a gate connected to the first output node; and
a sixth transistor connected between a line that applies a ground voltage and a fourth node, and includes a gate configured to receive the inverted input signal.
8 . The level shifter of claim 7 , wherein the third circuit further comprises:
a seventh transistor connected between the third node and the output node, and includes a gate configured to receive a first bias signal; and
a eighth transistor connected between the output node and the fourth node, and includes a gate configured to receive a second bias signal different from the first bias signal.
9 . The level shifter of claim 8 , further comprising:
a ninth transistor that includes a gate configured to receive the first bias signal, is connected to the output node, and is configured to adjust a lower limit of a voltage level of the output node to be equal to or higher than a voltage level of the first bias signal.
10 . The level shifter of claim 8 , further comprising:
a tenth transistor that includes a gate configured to receive the second bias signal, is connected to the output node, and is configured to adjust an upper limit of the voltage level of the output node to be equal to or lower than the voltage level of the second bias signal.
11 . The level shifter of claim 1 , further comprising:
a third circuit configured to pull up an output node that is configured to output an output signal, to the supply voltage, based on a voltage level of the second output node, and pull down the output node based on the input signal.
12 . The level shifter of claim 1 , further comprising:
a third circuit configured to pull up the second output node to the supply voltage based on a voltage level of the first output node, and pull up the first output node to the supply voltage based on a voltage level of the second output node.
13 . A memory device comprising:
a row address decoder including a level shifter configured to:
generate an output signal by pulling up a voltage level of a first node to a first voltage level different from a voltage level of a first input signal by a pull-up current flowing through a first path, when receiving a first input signal;
shut off the pull-up current by a first driving current flowing through a second path different from the first path, when receiving a second input signal which is an inverted signal of the first input signal; and
pull down the voltage level of a first node to a second voltage level different from the first voltage level by a second driving current flowing through a third path, when receiving the second input signal and shutting off the pull-up current; and
a memory cell array including a word line configured to receive the output signal, and a plurality of memory cells connected to the word line,
wherein the first driving current and the second driving current are configured to minimize a current fighting between the pull-up current and a pull-down current.
14 . The memory device of claim 13 , wherein the level shifter is configured to pull up the voltage level of the first node to the first voltage level by a fourth current flowing through a fourth path, when receiving the first input signal.
15 . The memory device of claim 14 , wherein the first driving current also configured to shut off the fourth current.