IP Library › Granted Patent US 12712535
Granted Patent B2
US 12712535 · App. 18/791,112 · Granted Aug 18, 2026

Integrated circuit and method of forming the same

Inventors: Yueh Chiang (Hsinchu, TW); Shang-Hsuan Chiu (Hsinchu, TW); Ming-Xiang Lu (Hsinchu, TW); Kuang-Ching Chang (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
H03K3/35625G06F30/39H03K3/356139H03K19/20H10D84/856H10D89/10
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Quick Facts
Patent No.
US 12712535
App. No.
18/791,112
Granted
Aug 18, 2026
Kind
B2
Abstract

A flip-flop includes a first input circuit, a first NAND logic gate, a first stacked gate circuit, a first NOR logic gate, a first output circuit and a first set buffer circuit. The first input circuit is coupled to a first node. The first NAND logic gate is coupled between the first and second node. The first stacked gate circuit is coupled between the first and third node, and configured to generate a third signal responsive to the first signal. The first NOR logic gate is coupled between the third node and a fourth node. The first output circuit is coupled to the fourth node. The first set buffer circuit is coupled to the first NOR logic gate.

Claims (75)

1 . A flip-flop comprising:

a first input circuit coupled to a first node, and being configured to generate a first signal responsive to at least a first data signal, a first clock signal, or a second clock signal inverted from the first clock signal;

a first NAND logic gate coupled between the first node and a second node, and being configured to generate a second signal responsive to the first signal and a first set signal;

a first stacked gate circuit coupled between the first node and a third node, the first stacked gate circuit being configured to generate a third signal responsive to at least the first signal;

a first NOR logic gate coupled between the third node and a fourth node, and being configured to generate a fourth signal responsive to the third signal and a second set signal inverted from the first set signal;

a first output circuit coupled to the fourth node, and being configured to generate a first output signal responsive to the fourth signal; and

a first set buffer circuit coupled to the first NOR logic gate, the first set buffer circuit being configured to generate the second set signal responsive to the first set signal.

2 . The flip-flop of claim 1 , wherein the first input circuit comprises:

a first P-type transistor having a gate of the first P-type transistor configured to receive one of the first clock signal or the second clock signal, a source of the first P-type transistor coupled to a first intermediate node, and a drain of the first P-type transistor coupled with at least the first node; and

a first N-type transistor having a gate of the first N-type transistor configured to receive another of the first clock signal or the second clock signal, a source of the first N-type transistor coupled to a second intermediate node, and a drain of the first N-type transistor coupled with the first node.

3 . The flip-flop of claim 2 , wherein the first input circuit further comprises:

a second P-type transistor having a drain of the second P-type transistor, a gate of the second P-type transistor configured to receive a scan enable signal, and a source of the second P-type transistor coupled to a voltage supply;

a third P-type transistor having a gate of the third P-type transistor configured to receive the first data signal, a source of the third P-type transistor coupled to the drain of the second P-type transistor, and a drain of the third P-type transistor coupled with at least the first intermediate node and the source of the first P-type transistor;

a fourth P-type transistor having a drain of the fourth P-type transistor, a gate of the fourth P-type transistor configured to receive a first scan in signal, and a source of the fourth P-type transistor coupled to the voltage supply; and

a fifth P-type transistor having a gate of the fifth P-type transistor configured to receive an inverted scan enable signal, a source of the fifth P-type transistor coupled to the drain of the fourth P-type transistor, and a drain of the fifth P-type transistor coupled with at least the first intermediate node, the source of the first P-type transistor and the drain of the third P-type transistor.

4 . The flip-flop of claim 3 , wherein the first input circuit further comprises:

a second N-type transistor having a drain of the second N-type transistor, a gate of the second N-type transistor configured to receive the inverted scan enable signal, and a source of the second N-type transistor coupled to a reference voltage supply;

a third N-type transistor having a gate of the third N-type transistor configured to receive the first data signal, a source of the third N-type transistor coupled to the drain of the second N-type transistor, and a drain of the third N-type transistor coupled with at least the second intermediate node and the source of the first N-type transistor;

a fourth N-type transistor having a drain of the fourth N-type transistor, a gate of the fourth N-type transistor configured to receive the first scan in signal, and a source of the fourth N-type transistor coupled to the reference voltage supply; and

a fifth N-type transistor having a gate of the fifth N-type transistor configured to receive the scan enable signal, a source of the fifth N-type transistor coupled to the drain of the fourth N-type transistor, and a drain of the fifth N-type transistor coupled with at least the second intermediate node, the source of the first N-type transistor and the drain of the third N-type transistor,

wherein the flip-flop is a scan flip-flop.

5 . The flip-flop of claim 1 , wherein the first stacked gate circuit comprises:

a first P-type transistor having a drain of the first P-type transistor, a gate of the first P-type transistor configured to receive the first signal and being coupled to at least the first node, and a source of the first P-type transistor coupled to a voltage supply;

a second P-type transistor having a gate of the second P-type transistor configured to receive one of the first clock signal or the second clock signal, a source of the second P-type transistor coupled to the drain of the first P-type transistor, and a drain of the second P-type transistor coupled with at least the third node;

a first N-type transistor having a drain of the first N-type transistor, a gate of the first N-type transistor configured to receive the first signal and being coupled to at least the first node and the gate of the first P-type transistor, and a source of the first N-type transistor coupled to a reference voltage supply; and

a second N-type transistor having a gate of the second N-type transistor configured to receive another of the first clock signal or the second clock signal, a source of the second N-type transistor coupled to the drain of the first N-type transistor, and a drain of the second N-type transistor coupled with at least the third node and the drain of the second P-type transistor.

6 . The flip-flop of claim 1 , further comprising:

a first reverse stacked gate circuit coupled between the first node and the second node, the first reverse stacked gate circuit being configured to set the first signal responsive to the second signal; and

a second reverse stacked gate circuit coupled between the third node and the fourth node, the second reverse stacked gate circuit being configured to set the third signal responsive to the fourth signal.

7 . The flip-flop of claim 1 , wherein the first node and the second node are separated from each other by a first distance, and the third node and the fourth node are separated from each other by a second distance.

8 . The flip-flop of claim 7 , wherein the first distance is less than or equal to 100 nanometers, and the second distance is less than or equal to 100 nanometers.

9 . A flip-flop comprising:

a first input circuit coupled to a first node, and being configured to generate a first signal responsive to at least a first data signal, a first clock signal or a second clock signal inverted from the first clock signal;

a first NAND logic gate coupled between the first node and a second node, and being configured to generate a second signal responsive to the first signal and a first set signal;

a first stacked gate circuit coupled between the first node and a third node, the first stacked gate circuit being configured to generate a third signal responsive to at least the first signal;

a first NOR logic gate coupled between the third node and a fourth node, and being configured to generate a fourth signal responsive to the third signal and a second set signal inverted from the first set signal;

a first reverse stacked gate circuit coupled between the first node and the second node, the first reverse stacked gate circuit being configured to set the first signal responsive to the second signal; and

a first set buffer circuit coupled to the first NOR logic gate, the first set buffer circuit being configured to generate the second set signal responsive to the first set signal.

10 . The flip-flop of claim 9 , wherein the first input circuit comprises:

a first P-type transistor having a gate of the first P-type transistor configured to receive one of the first clock signal or the second clock signal, a source of the first P-type transistor coupled to a first intermediate node, and a drain of the first P-type transistor coupled with at least the first node; and

a first N-type transistor having a gate of the first N-type transistor configured to receive another of the first clock signal or the second clock signal, a source of the first N-type transistor coupled to a second intermediate node, and a drain of the first N-type transistor coupled with the first node.

11 . The flip-flop of claim 10 , wherein the first input circuit further comprises:

a second P-type transistor having a drain of the second P-type transistor, a gate of the second P-type transistor configured to receive a scan enable signal, and a source of the second P-type transistor coupled to a voltage supply;

a third P-type transistor having a gate of the third P-type transistor configured to receive the first data signal, a source of the third P-type transistor coupled to the drain of the second P-type transistor, and a drain of the third P-type transistor coupled with at least the first intermediate node and the source of the first P-type transistor;

a fourth P-type transistor having a drain of the fourth P-type transistor, a gate of the fourth P-type transistor configured to receive a first scan in signal, and a source of the fourth P-type transistor coupled to the voltage supply; and

a fifth P-type transistor having a gate of the fifth P-type transistor configured to receive an inverted scan enable signal, a source of the fifth P-type transistor coupled to the drain of the fourth P-type transistor, and a drain of the fifth P-type transistor coupled with at least the first intermediate node, the source of the first P-type transistor and the drain of the third P-type transistor.

12 . The flip-flop of claim 11 , wherein the first input circuit further comprises:

a second N-type transistor having a drain of the second N-type transistor, a gate of the second N-type transistor configured to receive the inverted scan enable signal, and a source of the second N-type transistor coupled to a reference voltage supply;

a third N-type transistor having a gate of the third N-type transistor configured to receive the first data signal, a source of the third N-type transistor coupled to the drain of the second N-type transistor, and a drain of the third N-type transistor coupled with at least the second intermediate node and the source of the first N-type transistor;

a fourth N-type transistor having a drain of the fourth N-type transistor, a gate of the fourth N-type transistor configured to receive the first scan in signal, and a source of the fourth N-type transistor coupled to the reference voltage supply; and

a fifth N-type transistor having a gate of the fifth N-type transistor configured to receive the scan enable signal, a source of the fifth N-type transistor coupled to the drain of the fourth N-type transistor, and a drain of the fifth N-type transistor coupled with at least the second intermediate node, the source of the first N-type transistor and the drain of the third N-type transistor,

wherein the flip-flop is a scan flip-flop.

13 . The flip-flop of claim 12 , further comprising:

a first inverter coupled to the gate of the fifth P-type transistor and the gate of the second N-type transistor, and configured to receive the scan enable signal, and configured to generate the inverted scan enable signal.

14 . The flip-flop of claim 9 , wherein the first stacked gate circuit comprises:

a first P-type transistor having a drain of the first P-type transistor, a gate of the first P-type transistor configured to receive the first signal and being coupled to at least the first node, and a source of the first P-type transistor coupled to a voltage supply;

a second P-type transistor having a gate of the second P-type transistor configured to receive one of the first clock signal or the second clock signal, a source of the second P-type transistor coupled to the drain of the first P-type transistor, and a drain of the second P-type transistor coupled with at least the third node;

a first N-type transistor having a drain of the first N-type transistor, a gate of the first N-type transistor configured to receive the first signal and being coupled to at least the first node and the gate of the first P-type transistor, and a source of the first N-type transistor coupled to a reference voltage supply; and

a second N-type transistor having a gate of the second N-type transistor configured to receive another of the first clock signal or the second clock signal, a source of the second N-type transistor coupled to the drain of the first N-type transistor, and a drain of the second N-type transistor coupled with at least the third node and the drain of the second P-type transistor.

15 . The flip-flop of claim 9 , further comprising:

a second reverse stacked gate circuit coupled between the third node and the fourth node, the second reverse stacked gate circuit being configured to set the third signal responsive to the fourth signal.

16 . The flip-flop of claim 9 , further comprising:

a first clock circuit coupled to the first stacked gate circuit and the first reverse stacked gate circuit, and configured to receive a third clock signal, and configured to generate the first clock signal.

17 . The flip-flop of claim 16 , further comprising:

a second clock circuit coupled to the first clock circuit, the first stacked gate circuit and the first reverse stacked gate circuit, and configured to receive the first clock signal, and configured to generate the second clock signal.

18 . The flip-flop of claim 9 , wherein the first node and the second node are separated from each other by a first distance, and the third node and the fourth node are separated from each other by a second distance.

19 . The flip-flop of claim 18 , wherein the first distance is less than or equal to 100 nanometers, and the second distance is less than or equal to 100 nanometers.

20 . A flip-flop comprising:

a first input circuit coupled to a first node, and being configured to generate a first signal responsive to at least a first data signal, a first clock signal, or a second clock signal inverted from the first clock signal;

a first NAND logic gate coupled between the first node and a second node, and being configured to generate a second signal responsive to the first signal and a first set signal;

a first stacked gate circuit coupled between the first node and a third node, the first stacked gate circuit being configured to generate a third signal responsive to at least the first signal;

a first NOR logic gate coupled between the third node and a fourth node, and being configured to generate a fourth signal responsive to the third signal and a second set signal inverted from the first set signal;

a first reverse stacked gate circuit coupled between the first node and the second node, the first reverse stacked gate circuit being configured to set the first signal responsive to the second signal;

a first output circuit coupled to the fourth node, and being configured to generate a first output signal responsive to the fourth signal; and

a first set buffer circuit coupled to the first NOR logic gate, the first set buffer circuit being configured to generate the second set signal responsive to the first set signal.