Impedance calibration for SERDES transmitter driver

1 . A calibration circuit in an output driver comprising:

a first section that includes:

a first plurality of transistors powered by a first power rail;

a first error amplifier having a first input coupled to a first reference voltage source, a second input coupled to a feedback signal provided by an output of the first plurality of transistors and an output coupled to a gate of each transistor in the first plurality of transistors; and

a variable resistor coupled to the output of each transistor in the first plurality of transistors;

a second section that includes:

a second plurality of transistors powered by the first power rail;

a third plurality of transistors powered by the first power rail;

a replica driver stage coupled between the first power rail and ground through the second plurality of transistors, the replica driver stage comprising one or more replicas of a driver segment in the output driver;

a second error amplifier having a first input coupled to a second reference voltage source, a second input coupled to a node through which the output of the second plurality of transistors is coupled to the replica driver stage, and an output coupled to a gate of each transistor in the second plurality of transistors and a gate of each transistor in the third plurality of transistors; and

a fourth plurality of transistors that is included in a current mirror and configured to receive a current from the third plurality of transistors; and

a third section that includes:

a current comparator; and

a fifth plurality of transistors powered by the first power rail, each transistor in the fifth plurality of transistors having a gate that is coupled to the output of the first error amplifier, wherein an output of the fifth plurality of transistors is coupled to a first input of the current comparator; and

at least one mirror transistor configured to provide an output of the current mirror to a second input of the current comparator.

2 . The calibration circuit of claim 1 , wherein the first reference voltage source comprises:

a current source coupled between the first power rail and ground through a programmable resistor,

wherein the first input of the first error amplifier is coupled to a node through which the current source is coupled to the programmable resistor.

3 . The calibration circuit of claim 2 , wherein the programmable resistor is configured to provide a voltage at the node that is equal to voltage of a second power rail, and wherein the first power rail and second power rail deliver power at different voltages.

4 . The calibration circuit of claim 1 , wherein the variable resistor is configured to provide a resistance that represents or matches a nominal terminal impedance specified for the output driver.

5 . The calibration circuit of claim 1 , wherein amplitude of current provided to the first input of the current comparator is a multiple (P/Q) of the amplitude of current flowing in the variable resistor.

6 . The calibration circuit of claim 5 , wherein the multiple of the amplitude is defined by a ratio of number (P) of transistors in the first plurality of transistors to number (Q) of transistors in the fifth plurality of transistors.

7 . The calibration circuit of claim 1 , wherein the second reference voltage source is configured to maintain the first input of the second error amplifier at a voltage that is equal to voltage of a second power rail.

8 . The calibration circuit of claim 1 , wherein amplitude of current provided to the second input of the current comparator is a multiple of the amplitude of current flowing in the replica driver stage.

9 . The calibration circuit of claim 1 , wherein the second plurality of transistors includes a first number (L) of transistors, the third plurality of transistors includes a second number (S) of transistors, the fourth plurality of transistors includes a third number (M) of transistors and the replica driver stage includes a number (N) replicas of the driver segment.

10 . The calibration circuit of claim 9 , wherein the variable resistor is configured to provide a first resistance (R Target ), the driver segment in the output driver has a second resistance (R LSB ) and wherein:

S

≈

L

×

M

N

×

R

LSB

R

Target

,

when an amplitude of the current provided to the first input of the current comparator equals an amplitude of the current provided to the second input of the current comparator.

11 . An apparatus comprising:

means for generating a first current that is representative of current flowing through a termination impedance of an output driver;

means for generating a second current that is representative of current flowing through a replica driver comprising one or more replicas of a driver segment in the output driver; and

a current comparator configured to compare the first current and the second current, wherein the means for generating the second current comprises:

a first plurality of transistors powered by a first power rail;

a second plurality of transistors powered by the first power rail;

a replica driver stage coupled between the first power rail and ground through the first plurality of transistors, the replica driver stage comprising one or more replicas of a driver segment in the output driver;

an error amplifier having a first input coupled to a reference voltage source, a second input coupled to a node through which the output of the first plurality of transistors is coupled to the replica driver stage, and an output coupled to a gate of each transistor in the first plurality of transistors and a gate of each transistor in the second plurality of transistors;

a third plurality of transistors that is included in a current mirror and configured to receive a current from the second plurality of transistors; and

at least one mirror transistor configured to provide an output of the current mirror to a second input of the current comparator.

12 . The apparatus of claim 11 , wherein the reference voltage source is configured to maintain the first input of the error amplifier at a voltage that is equal to voltage of a second power rail.

13 . The apparatus of claim 11 , further comprising:

means for scaling the second current such that amplitude of current flowing through the at least one mirror transistor is a multiple of the amplitude of current flowing in the replica driver stage.

14 . The apparatus of claim 11 , wherein the first plurality of transistors includes a first number (L) of transistors, the second plurality of transistors includes a second number (S) of transistors, the third plurality of transistors includes a third number (M) of transistors and the replica driver stage includes a number (N) replicas of the driver segment, wherein a nominal terminal resistance (R Target ) is defined for the output driver, wherein each driver segment in the output driver has an output resistance (R LSB ) and wherein:

S

≈

L

×

M

N

×

R

LSB

R

Target

,

when the amplitude of the current provided to the first input of the current comparator equals the amplitude of the current provided to the second input of the current comparator.

15 . A method for calibrating an output driver, comprising:

generating a first current that is representative of current flowing through a termination impedance of an output driver;

generating a second current that is representative of current flowing through a replica driver stage comprising one or more replicas of a driver stage in a driver segment in the output driver; and

comparing the first current and the second current using a current comparator, wherein generating the second current comprises:

controlling gate voltage of a first plurality of transistors configured to provide a reference current to the replica driver stage to maintain a predefined voltage across the replica driver stage,

wherein the gates of the first plurality of transistors are coupled to gates of a second plurality of transistors that is configured to provide a scaled version of the reference current to a third plurality of transistors that is included in a current mirror, and wherein the second current is received from the current comparator.

16 . The method of claim 15 , wherein the first plurality of transistors and the second plurality of transistors receive power from a first power rail, wherein the predefined voltage corresponds to voltage at which a second power rail delivers power.

17 . The method of claim 16 , wherein the first power rail and second power rail deliver power at different voltages.

18 . The method of claim 15 , further comprising:

scaling the second current such that amplitude of the second current is a multiple of the amplitude of current flowing in the replica driver stage.

19 . The method of claim 15 , wherein the first plurality of transistors includes a first number (L) of active transistors, the second plurality of transistors includes a second number (S) of active transistors, the third plurality of transistors includes a third number (M) of active transistors and the replica driver stage includes a number (N) replicas of the driver segment, wherein a nominal terminal resistance (R Target ) is defined for the output driver, wherein each driver segment in the output driver has an output resistance (R LSB ) and wherein:

S

≈

L

×

M

N

×

R

LSB

R

Target

,

when the amplitude of the current provided to the first input of the current comparator equals the amplitude of the current provided to the second input of the current comparator.

20 . The method of claim 19 , further comprising:

iteratively increasing or decreasing the number of active transistors in the second plurality of transistors until signaling state of an output of the current comparator changes.