IP Library › Granted Patent US 12712545
Granted Patent B2
US 12712545 · App. 18/599,361 · Granted Aug 18, 2026

Multi-channel multiplexer

Inventors: Nitin Agarwal (Bengaluru, IN); Kunal Suresh Karanjkar (Bengaluru, IN); Venkata Ramanan R (Bengaluru, IN)
Assignee: TEXAS INSTRUMENTS INCORPORATED
H03K17/693H03F3/72H03K17/005H03K17/102
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Quick Facts
Patent No.
US 12712545
App. No.
18/599,361
Granted
Aug 18, 2026
Kind
B2
Abstract

A circuit includes a first switch assembly having a first input node and a first output node, and a second switch assembly having a second input node and a second output node. The circuit further includes a third switch assembly an operational amplifier, and a buffer. The third switch assembly has a third input node and a third output node. The third input node is coupled to the second output node, and the third output node is coupled to the first output node. The buffer has a buffer input and a buffer output. The buffer input is coupled to an input stage of the operational amplifier. The buffer output is coupled to the third switch assembly.

Claims (48)

1 . A circuit, comprising:

a first switch assembly having a first switch, a second switch, and a third switch, the first and second switches coupled in series through an internal terminal, the third switch coupled to the internal terminal, the third switch configured to be turned off based on the first and second switches being turned on, and the third switch configured to be turned on based on the first and second switches being turned off;

a second switch assembly having a first switch, a second switch with a first terminal and a second terminal, and a third switch, the first terminal of the second switch directly coupled in series to the first switch through an internal terminal, the third switch coupled to the internal terminal, the third switch configured to be turned off based on the first and second switches being turned on, the third switch configured to be turned on based on the first and second switches being turned off, and the first and second switches configured to be turned off based on the first and second switches of the first switch assembly being turned on;

a buffer having an input and an output, the input coupled to the second switch of the first switch assembly; and

a third switch assembly having a first switch with a first terminal and a second terminal, a second switch, and a third switch, the second terminal of the first switch directly coupled in series to the second switch through an internal terminal, the third switch between the internal terminal and the output of the buffer, the first terminal of the first switch directly coupled to the second terminal of the second switch of the second switch assembly, the second switch further coupled to the input of the buffer, and the first and second switches configured to be turned on based on the first and second switches of the second switch assembly being turned on.

2 . The circuit of claim 1 , wherein the buffer comprises a unit gain buffer.

3 . The circuit of claim 1 , wherein the buffer comprises:

a first transistor, a second transistor, and a third transistor coupled in series, the second transistor coupled between the first and third transistors, and a gate of the second transistor coupled to a drain of the second transistor.

4 . The circuit of claim 3 , wherein the first and second transistors are p-type MOS transistors, and the third transistor is a n-type MOS transistor.

5 . The circuit of claim 1 , further comprising:

an operational amplifier having an input coupled to the input of the buffer.

6 . The circuit of claim 1 , wherein the second switch of the first switch assembly comprises:

a first transistor having a drain and a source; and

a second transistor having a drain and a source, the drain coupled to the drain of the first transistor, and the source coupled to the source of the first transistor.

7 . The circuit of claim 6 , wherein the first transistor is a p-type MOS transistor, and the second transistor is a n-type MOS transistor.

8 . The circuit of claim 1 , further comprising:

a controller configured to turn on or off the first, second, and third switches of the first and second switch assemblies.

9 . A system, comprising:

a first switch assembly having a first switch, a second switch, and a third switch, the first and second switches coupled in series through an internal terminal, and the third switch coupled to the internal terminal;

a second switch assembly having a first switch, a second switch with a first terminal and a second terminal, and a third switch, the first terminal of the second switch directly coupled in series to the first switch through an internal terminal, and the third switch coupled to the internal terminal;

a buffer having an input and an output, the input coupled to the second switch of the first switch;

a third switch assembly having a first switch with a first terminal and a second terminal, a second switch, and a third switch, the second terminal of the first switch directly coupled in series to the second switch through an internal terminal, the third switch between the internal terminal and the output of the buffer, the first terminal of the first switch directly coupled to the second terminal of the second switch of the second switch assembly, and the second switch further coupled to the input of the buffer; and

a controller configured to:

turn off the third switch of the first switch assembly based on the first and second switches of the first switch assembly being turned on, and turn on the third switch of the first switch assembly based on the first and second switches of the first switch assembly being turned off;

turn off the third switch of the second switch assembly based on the first and second switches of the second switch assembly being turned on, and turn on the third switch of the second switch assembly based on the first and second switches of the second switch assembly being turned off;

turn off the first and second switches of the second switch assembly based on the first and second switches of the first switch assembly being turned on; and

turn on the first and second switches of the third switch assembly and turn off the third switch of the third switch assembly based on the first and second switches of the second switch assembly being turned on.

10 . The system of claim 9 , wherein the buffer comprises a unit gain buffer.

11 . The system of claim 9 , wherein the buffer comprises:

a first transistor, a second transistor, and a third transistor coupled in series, the second transistor coupled between the first and third transistors, and a gate of the second transistor coupled to a drain of the second transistor.

12 . The system of claim 11 , wherein the first and second transistors are p-type MOS transistors, and the third transistor is a n-type MOS transistor.

13 . The system of claim 9 , further comprising:

an operational amplifier having an input coupled to the input of the buffer.

14 . The system of claim 9 , wherein the second switch of the first switch assembly comprises:

a first transistor having a drain and a source; and

a second transistor having a drain and a source, the drain coupled to the drain of the first transistor, the source coupled to the source of the first transistor.

15 . The system of claim 14 , wherein the first transistor is a p-type MOS transistor, and the second transistor is a n-type MOS transistor.

16 . A circuit, comprising:

a first switch assembly having a first switch with a first terminal and a second terminal, a second switch with a first terminal and a second terminal, and a third switch with a first terminal and a second terminal, the first terminal of the first switch directly coupled to a first input, the second terminal of the first switch directly coupled in series to the first terminal of the second switch through an internal terminal, and the first terminal of the third switch directly coupled to the internal terminal;

a second switch assembly having a first switch with a first terminal and a second terminal, a second switch with a first terminal and a second terminal, and a third switch with a first terminal and a second terminal, the first terminal of the first switch directly coupled to a second input, the first terminal of the second switch directly coupled in series to the first switch through an internal terminal, and the first terminal of the third switch directly coupled to the internal terminal;

a third switch assembly having a first switch with a first terminal and a second terminal, a second switch with a first terminal and a second terminal, and a third switch with a first terminal and a second terminal, the second terminal of the first switch directly coupled in series to the second switch through an internal terminal, the first terminal of the third switch directly coupled to the internal terminal, the first terminal of the first switch directly coupled to the second terminal of the second switch of the second switch assembly, and the first and second switches are configured to be turned on based on the first and second switches of the second switch assembly being turned on; and

a buffer having an input and an output, the input directly coupled to the second terminal of the second switch of the first switch assembly and the second terminal of the second switch of the third switch assembly, and the output directly coupled to the second terminal of the third switch of the third switch assembly.

17 . The circuit of claim 16 , wherein the buffer comprises a unit gain buffer.

18 . The circuit of claim 16 , wherein the buffer comprises:

a first transistor, a second transistor, and a third transistor coupled in series, the second transistor coupled between the first and third transistors, a gate of the second transistor coupled to a drain of the second transistor.

19 . The circuit of claim 16 , wherein the second terminal of the third switch of the first switch assembly and the second terminal of the third switch of the second switch assembly are configured to be directly coupled to ground.

20 . The circuit of claim 16 , further comprising:

an operational amplifier having an input coupled to the input of the buffer.