Integrated circuit with ESD protection circuit

1 . An integrated circuit, comprising:

a first active region of a first conductivity type coupled to a first voltage terminal and corresponding to a first terminal of a first transistor and a first terminal of a second transistor included in an inverter of a level shifter circuit, wherein the first transistor is configured to discharge electrostatic charges to the first voltage terminal; and

second and third active regions, corresponding to a third transistor, of a second conductivity type different from the first conductivity type, wherein the second active region is coupled to a second voltage terminal, and the third active region is coupled to a terminal, different from the second voltage terminal, of the level shifter circuit,

wherein the third transistor is configured to transmit a first supply voltage from the second voltage terminal for the integrated circuit.

2 . The integrated circuit of claim 1 , further comprising:

a fourth active region of the first conductivity type, wherein the fourth active region corresponds to a second terminal of the first transistor, wherein the fourth active region is disposed in an active area extending in a first direction; and

a conductive line extending in a second direction different from the first direction to couple the third active region to the fourth active region.

3 . The integrated circuit of claim 1 , further comprising:

a fourth active region of the first conductivity type, wherein the fourth active region corresponds to a second terminal of the first transistor, wherein the fourth active region is disposed in an active area extending in a first direction;

first and second gates extending in a second direction different from the first direction, wherein the second active region is interposed between the first and second gates; and

a conductive line including a first portion extending in the second direction to couple the second gate to the fourth active region.

4 . The integrated circuit of claim 3 , further comprising:

a third gate coupled to a second portion, extending in the first direction, of the conductive line, wherein the fourth active region is interposed between the first and third gates.

5 . The integrated circuit of claim 1 , further comprising:

a fourth active region of the second conductivity type in a well of the first conductivity type, corresponding to a terminal of a fourth transistor, of the second conductivity type;

a gate corresponding to the first transistor; and

a conductive trace configured to couple the fourth active region and the gate.

6 . The integrated circuit of claim 1 , further comprising:

a first gate that extends in a first direction and corresponds to the third transistor; and

a second gate extending in the first direction,

wherein the first and second gates are aligned along the first direction and are coupled together for transmitting the first supply voltage.

7 . The integrated circuit of claim 6 , further comprising:

a third gate extending in the first direction and corresponding to a fourth transistor;

a fourth active region, corresponding to a fifth transistor, of the first conductivity type; and

a conductive line coupled to the third gate and the fourth active region and configured to transmit a second supply voltage.

8 . The integrated circuit of claim 1 , further comprising:

a fourth active region corresponding to a second terminal of the first transistor;

fifth and sixth active regions of the first conductivity type, wherein the fifth active region is coupled to the first voltage terminal;

a conductive structure coupled to the fourth active region, the sixth active region, and a third voltage terminal different from the first voltage terminal,

wherein the first active region receives the first supply voltage, the fourth and sixth active regions receive a second supply voltage, and

the first and second supply voltages are different from each other.

9 . An integrated circuit, comprising:

a level shifter circuit, comprising:

a first transistor and a second transistor separate from each other in a first direction in a layout view, wherein gate terminals of the first and second transistors are coupled together; and

an ESD (electrostatic discharge) protection circuit, coupled to an internal terminal of the level shifter circuit and configured to discharge electrostatic charges between a first voltage terminal and a second voltage terminal different from the first voltage terminal,

wherein the ESD protection circuit comprises a third transistor having first and second active regions, wherein the first active region is coupled to the internal terminal of the level shifter circuit and the second active region is coupled to the second voltage terminal,

wherein, in the layout view, the third transistor is arranged between the first transistor and the second transistor in the first direction.

10 . The integrated circuit of claim 9 , wherein the ESD protection circuit further comprises:

a fourth transistor having a third active region coupled to the first active region and a fourth active region coupled to the first voltage terminal,

wherein in the layout view the fourth transistor is arranged between the first transistor and the second transistor in the first direction.

11 . The integrated circuit of claim 10 , wherein the ESD protection circuit further comprises:

a fifth transistor having a gate and a fifth active region that are coupled to a gate of the fourth transistor,

wherein, in the layout view, the fifth transistor is arranged between the third transistor and the second transistor in the first direction.

12 . The integrated circuit of claim 9 , wherein the level shifter circuit further includes:

a fourth transistor coupled to the second transistor and separate from the second transistor in a second direction different from the first direction in the layout view,

wherein the first to third transistors are in a first voltage domain, and the fourth transistor is in a second voltage domain different from the first voltage domain.

13 . The integrated circuit of claim 9 , wherein the ESD protection circuit further comprises:

a fourth transistor, wherein a gate of the fourth transistor is coupled to a gate of the third transistor and the internal terminal of the level shifter circuit,

wherein the third and fourth transistors are aligned with each other along a second direction different from the first direction.

14 . The integrated circuit of claim 9 , wherein the ESD protection circuit further comprises:

a fourth transistor, wherein a first terminal of the fourth transistor is coupled to the second voltage terminal, a second terminal of the fourth transistor is coupled to the first active region, and the third and fourth transistor are separate from each other along the first direction in the layout view; and

a fifth transistor, wherein a terminal of the fifth transistor is coupled to a gate of the fourth transistor,

wherein the fourth and fifth transistors are aligned with each other along a second direction different from the first direction.

15 . The integrated circuit of claim 9 , wherein the ESD protection circuit further comprises:

a fourth transistor having third and fourth active regions, wherein the third active region is coupled to a third voltage terminal, and the fourth active region is coupled to the second active region and the second voltage terminal,

wherein in the layout view the fourth transistor is arranged between the third transistor and the second transistor in the first direction.

16 . The integrated circuit of claim 9 , wherein the ESD protection circuit is further configured to adjust a voltage level at the internal terminal of the level shifter circuit to have a voltage of the first voltage terminal or a voltage of the second voltage terminal.

17 . An integrated circuit, comprising:

a first active region of a first conductivity type coupled to a first voltage terminal and corresponding to a first terminal of a first transistor and a first terminal of a second transistor included in an inverter of a level shifter circuit;

a second active region of the first conductivity type coupled to a terminal of the level shifter circuit and corresponding to a second terminal of the first transistor; and

a third active region of a second conductivity type coupled to the terminal and corresponding to a first terminal of a third transistor, wherein the second conductivity type is different from the first conductivity type;

wherein the second terminal of the first transistor is coupled to the first terminal of the third transistor.

18 . The integrated circuit of claim 17 , further comprising:

a fourth active region of the second conductivity type coupled to a second voltage terminal and corresponding to a second terminal of the third transistor.

19 . The integrated circuit of claim 17 , wherein the first and second active regions are disposed in a first active area extending in a first direction, and the third active region is disposed in a second active area extending in the first direction;

wherein the first and second active areas are separated from each other in a second direction different from the first direction.

20 . The integrated circuit of claim 19 , further comprising:

a conductive line extending in the second direction to couple the second active region to the third active region.