Clock synthesizer
View Patent ↗A clock synthesizer is provided. The Clock synthesizer includes a Phase Locked Loop (PLL) configured to generate a clock signal based on a reference signal. A clock buffer is connected to the PLL. The clock buffer is configured to store the clock signal. A Duty Cycle Controller and Phase Interpolator (DCCPI) circuit is connected to the clock buffer. The DCCPI circuit is configured to receive the clock signal from the clock buffer, adjust a duty cycle of the clock signal to substantially equal to 50%, perform phase interpolation on the clock signal, and provide the clock signal as an output after adjusting the duty cycle substantially equal to 50% and performing the phase interpolation.
1 . A clock synthesizer comprising:
a Duty Cycle Controller and Phase Interpolator (DCCPI) circuit, wherein the DCCPI circuit is configured to:
receive an input clock signal, and
provide an output clock signal as an output from the input signal;
a replica circuit connected to an output of the DCCPI circuit, wherein the replica circuit is operative to replicate the output clock signal and provide a replica clock signal;
a phase detection circuit connected to the replica circuit, wherein the phase detection circuit is operative to:
compare the replica clock signal with a reference clock signal, and
provide, to the DCCPI circuit, a voltage signal that represents a difference in phase between the replica clock signal and the reference clock signal; and
wherein the DCCPI circuit is operative to:
adjust a duty cycle of the input clock signal,
interpolate a phase value of the input clock signal based on the difference in the phase between the replica clock signal with the reference clock signal, wherein the DCCPI circuit being operative to interpolate the phase value comprises the DCCPI circuit being operative to shift a rising edge of the input clock signal, and
provide duty adjusted and phase interpolated input signal as the output clock signal.
2 . The clock synthesizer of claim 1 , wherein the DCCPI circuit comprises a phase interpolator and a voltage/current alternator, and wherein:
the phase interpolator is configured to interpolate the phase value of the input clock signal, and
the voltage/current alternator is configured to adjust a duty cycle of the clock signal based on a difference between an average Direct Current (DC) voltage value of the clock signal and an average DC voltage value of an inverted clock signal.
3 . The clock synthesizer of claim 2 , wherein the voltage/current alternator comprises a first cascade of transistors and a second cascade of transistors, wherein a number of switched on transistors in the first cascade of transistors are increased and a number of switched on transistors in the second cascade of transistors are decreased to decrease the duty cycle of the clock signal.
4 . The clock synthesizer of claim 3 , wherein each first transistors of the first cascade of transistors comprises p-channel Metal Oxide Semiconductor (PMOS) transistors, and wherein each second transistors of the second cascade of transistors comprises n-channel Metal Oxide Semiconductor (NMOS) transistors.
5 . The clock synthesizer of claim 2 , wherein the voltage/current alternator comprises a first cascade of transistors and a second cascade of transistors, wherein a number of switched on transistors in the first cascade of transistors are decreased and a number of switched on transistors in the second cascade of transistors are increased to increase the duty cycle of the clock signal.
6 . The clock synthesizer of claim 2 , further comprising a phase selector connected to the phase interpolator, wherein the phase selector is operative to:
select one or two phases of the input clock signal; and
provide the selected one or two phases of the input clock signal to the phase interpolator.
7 . The clock synthesizer of claim 1 , wherein the DCCPI circuit comprises:
a first Direct Current (DC) sampler operative to determine an average DC voltage value of an inverted input clock signal;
a second DC sampler operative to determine an average DC voltage value of the input clock signal;
an error amplifier connected to the first DC sampler and the second DC sampler, wherein the error amplifier is operative to determine the difference between the average DC voltage value of the inverted input clock signal and the average DC voltage value of the input clock signal; and
a voltage/current alternator connected to the error amplifier, and wherein the voltage/current alternator is operative to adjust the duty cycle of the input clock signal based on the difference between the average DC voltage value of the inverted input clock signal and the average DC voltage value of the input clock signal.
8 . A clock synthesizer comprising:
a Duty Cycle Controller and Phase Interpolator (DCCPI) circuit, wherein the DCCPI circuit is configured to:
receive an input clock signal,
perform phase interpolation on the input clock signal,
adjust a duty cycle of the input clock signal based on a difference between an average Direct Current (DC) voltage value of the clock signal and an average DC voltage value of an inverted clock signal, and
provide an output clock signal as an output after adjusting the duty cycle;
a replica circuit connected to the DCCPI circuit, wherein the replica circuit is operative to replicate the output clock signal and provide a replica clock signal;
a phase detection circuit connected to the replica circuit, wherein the phase detection circuit is operative to:
compare the replica clock signal with a reference clock signal, and
provide, to the DCCPI circuit, a voltage signal that represents a difference in phase between the replica clock signal and the reference clock signal; and wherein the DCCPI circuit is operative to:
interpolate a phase value of the input clock signal based on the difference in the phase between the replica clock signal with the reference clock signal, and
provide duty adjusted and phase interpolated input signal as the output clock signal.
9 . The clock synthesizer of claim 8 , wherein the DCCPI circuit comprises:
a first Direct Current (DC) sampler operative to determine an average DC voltage value of an inverted input clock signal;
a second DC sampler operative to determine an average DC voltage value of the clock signal;
an error amplifier connected to the first DC sampler and the second DC sampler, wherein the error amplifier is operative to determine the difference between the average DC voltage value of the inverted clock signal and the average DC voltage value of the clock signal; and
a voltage/current alternator connected to the error amplifier, and wherein the voltage/current alternator is operative to adjust the duty cycle of the input clock signal based on the difference between the average DC voltage value of the inverted clock signal and the average DC voltage value of the clock signal.
10 . The clock synthesizer of claim 8 , wherein the DCCPI circuit comprises a phase interpolator and a voltage/current alternator, and wherein:
the phase interpolator is configured to interpolate the phase value of the input clock signal, and
the voltage/current alternator is configured to adjust a duty cycle of the clock signal based on a difference between an average Direct Current (DC) voltage value of the input clock signal and an average DC voltage value of an inverted input clock signal.
11 . The clock synthesizer of claim 10 , wherein the voltage/current alternator comprises a first cascade of transistors and a second cascade of transistors, wherein a number of switched on transistors in the first cascade of transistors are increased and a number of switched on transistors in the second cascade of transistors are decreased to decrease the duty cycle of the clock signal.
12 . The clock synthesizer of claim 11 , wherein each first transistors of the first cascade of transistors comprises p-channel Metal Oxide Semiconductor (PMOS) transistors, and wherein each second transistors of the second cascade of transistors comprises n-channel Metal Oxide Semiconductor (NMOS) transistors.
13 . The clock synthesizer of claim 10 , wherein the voltage/current alternator comprises a first cascade of transistors and a second cascade of transistors, wherein a number of switched on transistors in the first cascade of transistors are decreased and a number of switched on transistors in the second cascade of transistors are increased to increase the duty cycle of the clock signal.
14 . The clock synthesizer of claim 10 , further comprising a phase selector connected to the phase interpolator, wherein the phase selector is operative to:
select one or two phases of the input clock signal; and
provide the selected one or two phases of the input clock signal to the phase interpolator.
15 . The clock synthesizer of claim 1 , wherein the DCCPI circuit being operative to interpolate the phase value comprises the DCCPI circuit being operative to shift a rising edge of the input clock signal.
16 . A method of synthesizing a clock signal, the method comprising:
replicating, by a replica circuit connected to an output of a Duty Cycle Controller and Phase Interpolator (DCCPI) circuit, an output clock signal of DCCPI circuit;
comparing, by a phase detection circuit connected to the replica circuit, the replica clock signal with a reference clock signal;
providing, by the phase detection circuit to the DCCPI circuit, a voltage signal that represents a difference in phase between the replica clock signal and the reference clock signal;
adjusting, by the DCCPI circuit, a duty cycle of the input clock signal;
interpolating, by the DCCPI circuit, a phase value of the input clock signal based on the difference in the phase between the replica clock signal with the reference clock signal, wherein interpolating the phase value comprises shifting a rising edge of the input clock signal; and
providing, by the DCCPI circuit, duty adjusted and phase interpolated input signal as the output clock signal.
17 . The method of claim 16 , wherein interpolating the phase value of the input clock signal comprises interpolating the phase value of the input clock signal to account for a time delay in distribution of the output clock signal in a clock tree.
18 . The method of claim 16 , further comprising:
determining, by an error amplifier of the DCCPI circuit, a difference between a Direct Current (DC) voltage value of the clock signal and a DC voltage value of an inverted clock signal; and
adjusting, by a voltage current alternator connected to the error amplifier of the DCCPI circuit, the duty cycle of the clock signal based on the determined difference between the DC voltage value of the clock signal and the DC voltage value of the inverted clock signal to substantially equal to 50%.
19 . The method of claim 18 , wherein determining the difference between the DC voltage value of the clock signal and the DC voltage value of the inverted clock signal comprises:
generating, by a first invertor connected to the phase interpolator, an inverted clock signal by inverting the clock signal;
determining, by a first Direct Current (DC) sampler connected to the first invertor, an average DC voltage value of the inverted clock signal;
generating, by a second invertor connected to the first invertor, the clock signal by inverting the inverted clock signal;
determining, by a second DC sampler connected to the second invertor, an average DC voltage value of the clock signal; and
determining, by the error amplifier connected to the first DC sampler and the second DC sampler, a difference between the average DC voltage value of the inverted clock signal and the average DC voltage value of the clock signal.
20 . The method of claim 16 , wherein the DCCPI circuit comprises a phase interpolator and a voltage/current alternator.