Phase alignment system and method

1 . A system for phase alignment, comprising:

a radio frequency integrated circuit (RFIC) having a phase locked loop (PLL) circuit and a missing pulse detection circuit, the missing pulse detection circuit configured to detect a missing pulse from a reference clock source and generate a detection pulse signal; and

a counter reset circuit connected to the missing pulse detection circuit, the counter reset circuit configured to generate a counter reset signal in response to the detection pulse signal, the counter reset signal configured to establish an absolute time and frequency reference for the PLL circuit.

2 . The system of claim 1 , wherein the PLL comprises a fractional-N PLL.

3 . The system of claim 1 , further comprising an intermediate frequency integrated circuit (IFIC) having a missing pulse generator circuit configured to generate a modified reference clock signal having at least one missing clock pulse.

4 . The system of claim 1 , wherein the missing pulse detection circuit comprises a delay line circuit, a detection circuit and the counter reset circuit.

5 . The system of claim 4 , wherein the delay line circuit comprises eight (8) delay line stages.

6 . The system of claim 5 , wherein the detection circuit comprises three (3) delay line stages.

7 . The system of claim 6 , further comprising a phase comparator and voltage generator circuit configured to compare an output of a first delay line stage with an output of a last delay line stage to generate a one cycle delayed version of the reference clock source.

8 . The system of claim 7 , wherein the one cycle delayed version of the reference clock controls the signal delay of the delay line stages in the delay line circuit and detection circuit.

9 . The system of claim 4 , wherein the counter reset circuit comprises an adder and a flip-flop.

10 . The system of claim 1 , wherein the counter reset signal is provided to a delta-sigma modulator (DSM) in the PLL circuit.

11 . The system of claim 1 , wherein the counter reset signal is simultaneously provided to a plurality of delta-sigma modulators (DSMs) in a plurality of PLL circuits.

12 . A method for phase alignment, comprising:

detecting a missing pulse in a clock signal;

generating a detection pulse signal; and

generating a counter reset signal to reset a counter in response to the detection pulse signal, wherein resetting the counter establishes an absolute time and frequency reference.

13 . The method of claim 12 , further comprising resetting a plurality of counters to establish an absolute frequency reference for a plurality of phase locked loop (PLL) circuits.

14 . The method of claim 13 , wherein the PLL circuit is located in a radio frequency integrated circuit (RFIC).

15 . The method of claim 13 , wherein the PLL circuit comprises a fractional-N PLL.

16 . The method of claim 13 , further comprising generating the clock signal having the missing pulse.

17 . A device, comprising:

means for detecting a missing pulse in a clock signal;

means for generating a detection pulse signal; and

means for generating a counter reset signal to reset a counter in response to the detection pulse signal, wherein resetting the counter establishes an absolute time and frequency reference.

18 . The device of claim 17 , further comprising means for resetting a plurality of counters to establish an absolute frequency reference for a plurality of phase locked loop (PLL) circuits.

19 . The device of claim 18 , wherein the PLL circuit is located in a radio frequency integrated circuit (RFIC).

20 . The device of claim 17 , wherein the PLL circuit comprises a fractional-N PLL.