Receiver circuit scheme capable of avoiding clock harmonic interferences and reducing phase errors to maintain demodulator capability

1 . A receiver circuit comprising:

a mixer for mixing a radio frequency signal with a local oscillator signal to generate an intermediate frequency signal;

an intermediate frequency processing circuit, coupled to the mixer, for generating a baseband signal according to the intermediate frequency signal; and

a receiver analog-to-digital converter (ADC), coupled to the intermediate frequency processing circuit, for sampling information of the baseband signal to convert the baseband signal into a digital reception signal according to a working sample rate;

wherein the working sample rate is dynamically switched between a first sample rate and a second sample rate which are adjacent to a target sample rate, to make a harmonic of the first sample rate be not in a specific channel frequency of the radio frequency signal and a harmonic of the second sample rate be not in the specific channel frequency of the radio frequency signal; and the first sample rate is lower than the target sample rate while the second sample rate is higher than the target sample rate.

2 . The receiver circuit of claim 1 , further comprising:

a specific oscillator for generating the target sample rate;

a frequency dividing circuit, for performing a first frequency division operation upon a frequency of the local oscillator signal based on a first division factor to generate the first sample rate, and for performing a second frequency division operation upon the frequency of the local oscillator signal based on a second division factor to generate the second sample rate; and

a selection circuit, coupled to the specific oscillator, the receiver ADC, and the frequency dividing circuit, for receiving the target sample rate from the specific oscillator and receiving one of the first sample rate and the second sample rate from the frequency dividing circuit, for outputting the first sample rate or the second sample rate into the receiver ADC when a channel frequency currently used by the receiver circuit is the specific channel frequency, and for outputting the target sample rate into the receiver ADC when the channel frequency currently used by the receiver circuit is not the specific channel frequency.

3 . The receiver circuit of claim 2 , wherein the first division factor and the second division factor are adjacent integers.

4 . The receiver circuit of claim 2 , wherein the frequency dividing circuit is used to generate the first sample rate into the selection circuit during a first cycle time and generate the second sample rate into the selection circuit during a second cycle time following the first cycle time.

5 . The receiver circuit of claim 4 , wherein the first cycle time and the second cycle time are determined based on a relation between a first absolute difference and a second absolute difference, and the first absolute difference is generated from a difference between the first sample rate and the target sample rate while the second absolute difference is generated from a difference between the second sample rate and the target sample rate.

6 . The receiver circuit of claim 5 , wherein the first cycle time is N times longer than the second cycle time when the second absolute difference is N times the first absolute difference, and N is a positive integer.

7 . The receiver circuit of claim 4 , wherein the frequency dividing circuit is used to alternatively generate the first sample rate into the selection circuit during the first cycle time and generate the second sample rate into the selection circuit during the second cycle time.

8 . A method of a receiver circuit comprising:

providing a mixer to mix a radio frequency signal with a local oscillator signal to generate an intermediate frequency signal;

providing an intermediate frequency processing circuit to generate a baseband signal according to the intermediate frequency signal;

using a receiver analog-to-digital converter (ADC) to sample information of the baseband signal to convert the baseband signal into a digital reception signal according to a working sample rate; and

dynamically switching the working sample rate between a first sample rate and a second sample rate which are adjacent to a target sample rate, to make a harmonic of the first sample rate be not in a specific channel frequency of the radio frequency signal and a harmonic of the second sample rate be not in the specific channel frequency of the radio frequency signal;

wherein the first sample rate is lower than the target sample rate while the second sample rate is higher than the target sample rate.

9 . The method of claim 8 , further comprising:

using a specific oscillator to generate the target sample rate;

performing a first frequency division operation upon a frequency of the local oscillator signal based on a first division factor to generate the first sample rate;

performing a second frequency division operation upon the frequency of the local oscillator signal based on a second division factor to generate the second sample rate;

using a selection circuit to receive the target sample rate from the specific oscillator and to receive one of the first sample rate and the second sample rate, to output the first sample rate or the second sample rate into the receiver ADC when a channel frequency currently used by the receiver circuit is the specific channel frequency and to output the target sample rate into the receiver ADC when the channel frequency currently used by the receiver circuit is not the specific channel frequency.

10 . The method of claim 9 , wherein the first division factor and the second division factor are adjacent integers.

11 . The method of claim 9 , further comprising:

generating the first sample rate into the selection circuit during a first cycle time and generating the second sample rate into the selection circuit during a second cycle time following the first cycle time.

12 . The method of claim 11 , further comprising:

determining the first cycle time and the second cycle time based on a relation between a first absolute difference and a second absolute difference;

wherein the first absolute difference is generated from a difference between the first sample rate and the target sample rate while the second absolute difference is generated from a difference between the second sample rate and the target sample rate.

13 . The method of claim 12 , wherein the first cycle time is N times longer than the second cycle time when the second absolute difference is N times the first absolute difference, and N is a positive integer.

14 . The method of claim 11 , further comprising:

alternatively generating the first sample rate into the selection circuit during the first cycle time and generating the second sample rate into the selection circuit during the second cycle time.