Digital-to-analog converter (DAC) with DAC element error matching
An example digital-to-analog converter (DAC) circuit may comprise a plurality of single-bit DAC elements, an encoder circuit, and a multiplexer circuit. The encoder circuit may be configured to generate a control signal, where a number of asserted bits in the control signal is based at least in part on a digital input signal and an asserted bit pattern of the control signal is based at least in part on a random signal. The multiplexer circuit may be configured to modify the control signal to generate a noise-corrected control signal having a noise-corrected bit pattern. The noise-corrected bit pattern may direct a first asserted bit of the noise-corrected control signal to activate a first single-bit DAC element and a second asserted bit of the noise-corrected control signal to activate a second single-bit DAC element, where the first single-bit DAC element and the second single-bit DAC element having respective errors that at least partially cancel.
1 . A digital-to-analog converter (DAC) circuit comprising:
a plurality of single-bit DAC elements, each respective single-bit DAC element of the plurality of single-bit DAC elements being configured to receive a single-bit digital input and generate a corresponding DAC element output;
an encoder circuit configured to generate a control signal, a number of asserted bits in the control signal being based at least in part on a digital input signal and a bit pattern of the control signal being based at least in part on a random signal, the encoder circuit being configured to generate the control signal such that values of the control signal having a first number of asserted bits include less than all bit patterns having the first number of asserted bits;
a multiplexer circuit electrically coupled between the encoder circuit and the plurality of single-bit DAC elements, the multiplexer circuit being configured to modify the control signal to generate a noise-corrected control signal having a noise-corrected bit pattern, the noise-corrected bit pattern directing a first asserted bit of the noise-corrected control signal to activate a first single-bit DAC element and a second asserted bit of the noise-corrected control signal to activate a second single-bit DAC element, the first single-bit DAC element and the second single-bit DAC element being preselected to have respective errors that at least partially cancel; and
a summer circuit configured to sum DAC element outputs of the plurality of single-bit DAC elements to generate an analog output signal.
2 . The DAC circuit of claim 1 , the first single-bit DAC element having an error greater than an average error of the plurality of single-bit DAC elements and the second single-bit DAC element having an error less than the average error of the plurality of single-bit DAC elements.
3 . The DAC circuit of claim 2 , the error of the first single-bit DAC element and the second single-bit DAC element being at least one of a gain error or a timing error.
4 . The DAC circuit of claim 1 , the first single-bit DAC element having a highest error among the plurality of single-bit DAC elements and the second single-bit DAC element having a lowest error among the plurality of single-bit DAC elements.
5 . The DAC circuit of claim 1 , the first single-bit DAC element and the second single-bit DAC element being the two single-bit DAC elements of the plurality of single-bit DAC elements having respective errors closest to zero.
6 . The DAC circuit of claim 1 , the encoder circuit comprising:
a most significant bit input for receiving a most significant bit of the digital input signal; and
a most significant bit swapper circuit configured to set a first portion of bits of the control signal equal to the most significant bit of the digital input signal when a first bit of the random signal is asserted and to set a second portion of bits of the control signal equal to the most significant bit of the digital input signal when the first bit of the random signal is not asserted.
7 . The DAC circuit of claim 6 the multiplexer circuit being configured to generate the noise-corrected control signal to map the first portion of bits of the control signal to a preselected portion of the plurality of single-bit DAC elements, the preselected portion of the plurality of single-bit DAC elements having respective errors that at least partially cancel.
8 . The DAC circuit of claim 1 , the encoder circuit comprising:
a least significant bit input for receiving a least significant bit of the digital input signal; and
a least significant bit swapper circuit configured to set a first bit of the control signal equal to the least significant bit of the digital input signal when a first bit of the random signal is asserted and to set a second bit of the control signal equal to the least significant bit of the digital input signal when the first bit of the random signal is not asserted.
9 . A method for converting a digital signal to an analog signal, the method comprising:
determining respective errors for a plurality of single-bit digital-to-analog converter (DAC) elements;
selecting a first pair of single-bit DAC elements of the plurality of single-bit DAC elements the first pair of single-bit DAC elements comprising a first single-bit DAC element and a second single-bit DAC element, the first pair of single-bit DAC elements being preselected to have respective errors that at least partially cancel;
generating a control signal such that values of the control signal having a first number of asserted bits include less than all bit patterns having the first number of asserted bits; and
configuring a multiplexer of a DAC circuit to convert a control signal to a noise-corrected control signal, the control signal being generated based at least in part on a digital input signal and a random signal such that values of the control signal having a first number of asserted bits include less than all bit patterns having the first number of asserted bits, the noise-corrected bit pattern being arranged to direct a first asserted bit of the noise-corrected control signal to activate the first single-bit DAC element and a second asserted bit of the noise-corrected control signal to activate the second single-bit DAC element.
10 . The method of claim 9 , the first single-bit DAC element having an error greater than an average error of the plurality of single-bit DAC elements and the second single-bit DAC element having an error less than the average error of the plurality of single-bit DAC elements.
11 . The method of claim 9 , the error of the first single-bit DAC element and the second single-bit DAC element being at least one of a gain error or a timing error.
12 . The method of claim 9 , the first single-bit DAC element and the second single-bit DAC element being the two single-bit DAC elements of the plurality of single-bit DAC elements having respective errors closest to zero.
13 . The method of claim 9 , further comprising selecting a second pair of single-bit DAC elements of the plurality of single-bit DAC elements, the second pair of single-bit DAC elements comprising a third single-bit DAC element and a fourth single-bit DAC element having respective errors that at least partially cancel.
14 . The method of claim 13 , the noise-corrected bit pattern being further arranged to direct a third asserted bit of the noise-corrected control signal to activate the third single-bit DAC element and a fourth asserted bit of the noise-corrected control signal to activate the fourth single-bit DAC element.
15 . The method of claim 9 , further comprising selecting a first set of four single-bit DAC elements, a sum of errors of the four single-bit DAC elements being less than a sum of error of absolute values for the four single-bit DAC elements.
16 . The method of claim 15 , the noise-corrected bit pattern being further arranged to direct for asserted bits of the noise-corrected control signal to activate the first set of four single-bit DAC elements.
17 . A digital-to-analog converter (DAC) circuit comprising:
a plurality of single-bit DAC elements, each respective single-bit DAC element of the plurality of single-bit DAC elements being configured to receive a single-bit digital input and generate a corresponding DAC element output;
means for generating a control signal, a number of asserted bits in the control signal being based at least in part on a digital input signal and an asserted bit pattern of the control signal being based at least in part on a random signal, the control signal being generated such that values of the control signal having a first number of asserted bits include less than all bit patterns having the first number of asserted bits;
means for modifying the control signal to generate a noise-corrected control signal having a noise-corrected bit pattern, the noise-corrected bit pattern directing a first asserted bit of the noise-corrected control signal to activate a first single-bit DAC element and a second asserted bit of the noise-corrected control signal to activate a second single-bit DAC element, the first single-bit DAC element and the second single-bit DAC element being preselected to have respective errors that at least partially cancel; and
means for summing DAC element outputs of the plurality of single-bit DAC elements to generate an analog output signal.
18 . The DAC circuit of claim 17 , the first single-bit DAC element having an error greater than an average error of the plurality of single-bit DAC elements and the second single-bit DAC element having an error less than the average error of the plurality of single-bit DAC elements.
19 . The DAC circuit of claim 18 , the error of the first single-bit DAC element and the second single-bit DAC element being at least one of a gain error or a timing error.
20 . The DAC circuit of claim 17 , the first single-bit DAC element having a highest error among the plurality of single-bit DAC elements and the single-bit DAC element having a lowest error among the plurality of single-bit DAC elements.