Method and device for correcting errors in resistive memories
View Patent ↗A device and a method for reading a code word in a resistive memory protected by an ECC where each memory cell includes resistive devices for storing a bit of a code word. The method allows the selection, as a function of the value of a syndrome, of a corrected word following a first decoding process without inversion of weak-bits or of a corrected word following a second decoding process with inversion of weak-bits. If the computed syndrome determines that the first decoding process has indicated an uncorrectable error or determines that the second decoding process has indicated neither an uncorrectable error nor an n-error (i.e., a maximum of n erroneous bits per code word), the selected word is the corrected word with inversion of the weak-bits. Otherwise, the selected word is the corrected word without inversion of the weak-bits.
1 . A device for reading a code word stored in a resistive memory where each memory cell comprises resistive devices for storing a bit of a code word, the reading device comprising:
means for measuring the resistance of each resistive device storing a bit of a code word to be read, and for identifying weak-bits;
means for carrying out, with an error-correcting code decoder having a maximum correction capacity of n erroneous bits, a first and a second process of decoding the code word, with the first and second decoding processes being carried out without and with inversion of the weak-bits, respectively;
means for determining, in each version of the decoded code word, information concerning the number of errors, with respect to errors that are detectable but uncorrectable according to the correction capacity of said error-correcting code and with respect to errors that are correctable according to the correction capacity of said error-correcting code and that affect a maximum number of erroneous bits; and
means for selecting the version of the decoded code word without inversion of weak-bits if the information concerning the number of errors for the version of the decoded code word without inversion of weak-bits does not provide a number of errors that is greater than n−1; or the version of the decoded code word with inversion of weak-bits if the information concerning the number of errors for the version of the decoded code word without inversion of weak-bits indicates a number of uncorrectable errors or if the information concerning the number of errors for the version of the decoded code word with inversion of weak-bits does not provide a number of errors that is greater than n−1 and the information does not indicate an uncorrectable error.
2 . The device according to claim 1 , wherein the means for measuring the resistance of each resistive device comprise means for measuring the resistance of each resistive device relative to a reference resistance value.
3 . The device according to claim 1 , wherein the means for measuring the resistance of each resistive device comprise means for measuring the resistance of each resistive device relative to two resistance values.
4 . The device according to claim 1 , wherein the means for identifying weak-bits comprise means for comparing the measured resistance of each resistive device with a resistance value that is slightly greater than the reference resistance value, and with a resistance value that is slightly less than the reference resistance value, and for identifying those bits with results from these resistance comparisons that are not identical.
5 . The device according to claim 1 , wherein the means for carrying out a first and a second process of decoding the code word comprise means for sequentially carrying out the first and the second decoding process.
6 . The device according to claim 1 , wherein the means for carrying out a first and a second process of decoding the code word comprise means for simultaneously carrying out the first and the second decoding process.
7 . The device according to claim 1 , wherein the error-correcting code is of the SEC, SEC-DED, DEC, DEC-TED, TEC, TEC-QED, QEC, QEC-QED type.
8 . The device according to claim 1 , wherein the error-correcting code has a minimum Hamming distance du between the code words that is equal to 2n+2.
9 . The device according to claim 8 , wherein the error-correcting code is of the DEC-TED type with a minimum Hamming distance d H between the code words that is equal to 2n+2=6, and wherein the means for determining, in each version of the decoded code word, whether a number of errors is greater than ‘n−1=1’ rely on the evaluation of the following equation:
alarm
DEC
-
TED
=
(
∑
v
_
∧
∨
D
2
)
∨
∨
D
3
.
10 . The device according to claim 8 , wherein the corrector code is of the TEC-QED type with a minimum Hamming distance d H between the code words that is equal to 2n+2=8, and wherein the means for determining, in each version of the decoded code word, whether a number of errors is greater than ‘n−1=2’ rely on the evaluation of the following equation:
alarm
TEC
-
QED
=
(
∑
v
∧
∨
D
3
′
)
∨
∨
D
4
.
11 . The device according to claim 8 , wherein the corrector code is of the QEC-QED type with a minimum Hamming distance d H between the code words that is equal to 2n+2=10, and wherein the means for determining, in each version of the decoded code word, whether a number of errors is greater than ‘n−1=3’ rely on evaluation of the following equation:
alarm
QEC
-
QED
=
[
∑
v
_
∧
(
∨
D
4
∨
∨
D
4
′
)
]
∨
∨
D
5
.
12 . An electronic system of the FPGA or ASIC type comprising a device according to claim 1 .
13 . A method for reading a code word stored in a resistive memory where each memory cell comprises resistive devices for storing a bit of a code word, the method comprising at least the following steps of:
measuring the resistance of each resistive device storing a bit of a code word to be read, and identifying weak-bits;
carrying out, using an error-correcting code decoder with a maximum correction capacity of n erroneous bits, a first and a second process of decoding the code word, with the first and the second decoding processes being carried out without and with inversion of the weak-bits, respectively;
determining, in each version of the decoded code word, information concerning the number of errors, with respect to errors that are detectable but uncorrectable according to the correction capacity of said error-correcting code and with respect to errors that are correctable according to the correction capacity of said error-correcting code and that affect a maximum number of erroneous bits; and
selecting the version of the decoded code word without inversion of weak-bits if the information concerning the number of errors for the version of the decoded code word without inversion of weak-bits does not provide a number of errors that is greater than n−1; or the version of the decoded code word with inversion of weak-bits if the information concerning the number of errors for the version of the decoded code word without inversion of weak-bits indicates a number of uncorrectable errors or if the information concerning the number of errors for the version of the decoded code word with inversion of weak-bits does not provide a number of errors that is greater than n−1 and the information does not indicate an uncorrectable error.
14 . The method according to claim 13 , wherein the decoding step involves sequentially carrying out a first decoding process without inversion of weak-bits and a second decoding process with inversion of weak-bits.
15 . The method according to claim 13 , wherein the decoding step involves simultaneously carrying out a first decoding process without inversion of weak-bits and a second decoding process with inversion of weak-bits.