Link monitoring and indication of potential link failure
Examples described herein relate to a physical layer interface (PHY) that includes circuitry configured to autonomously measure for signal degradation by a baseline measurement of parameters and one or more subsequent measurements of parameters to indicate if link loss is expected.
1 . An apparatus comprising:
one or more slicers to provide data and error; and
a physical layer interface (PHY) comprising:
a serializer-deserializer (SerDes) device comprising a plurality of decision feedback equalizer (DFE) taps, and
circuitry, coupled to the SerDes device, configured to autonomously measure for signal degradation and to indicate if link loss is expected to occur based on a baseline measurement of parameters and one or more subsequent measurements of parameters, wherein:
the parameters comprise inter symbol interference (ISI) values measured from one or more of the plurality of DFE taps,
the circuitry comprises an integrator to sum the ISI values for one or more of the plurality of DFE taps, and
the link loss is expected to occur based on the sum of the ISI data values for the one or more of the plurality of DFE taps.
2 . The apparatus of claim 1 , wherein the parameters comprise one or more of: eye height, signal to noise ratio (SNR), phase lock loop (PLL) lock range, phase alignment values, equalizer coefficients, bias currents measured by an on-die analog-to-digital (A/D) converter, offset cancellation parameters raw bit error rate (BER) error dependence statistics, and/or counter values of corrected and uncorrected Forward Error Correction (FEC) values.
3 . The apparatus of claim 1 , wherein the circuitry is configured to adjust an interval of parameter measurements based on link loss being expected.
4 . The apparatus of claim 1 , wherein the circuitry is to indicate a potential connector dislocation based on changes to ISI data.
5 . The apparatus of claim 4 , wherein to indicate a potential connector dislocation based on changes to ISI data, the circuitry is to:
store a baseline ISI data for connector reflections;
measure ISI data for connector reflections; and
indicate a potential connector dislocation based on measured ISI data and baseline ISI data.
6 . The apparatus of claim 5 , wherein ISI data for connector reflections is based on one or more particular connections identified based on time-domain reflectometry (TDR).
7 . The apparatus of claim 1 , comprising:
a network interface device comprising the PHY, wherein the network interface device comprises:
one or more ports coupled to the PHY;
circuitry to perform media access control (MAC) operations; and
packet processing circuitry coupled to the circuitry to perform MAC operations.
8 . The apparatus of claim 1 , comprising:
a host system communicatively coupled to the PHY, wherein the host system is to receive the indication if link loss is expected and perform one or more remedial actions.
9 . At least one non-transitory computer-readable medium comprising instructions stored thereon, that if executed by one or more processors cause the one or more processors to:
configure circuitry to autonomously measure for signal degradation at a physical layer interface (PHY) and to indicate if link loss is expected to occur based on a baseline measurement of parameters and one or more subsequent measurements of parameters wherein the parameters comprise inter symbol interference (ISI) values measured from one or more of a plurality of decision feedback equalizer (DFE) taps of a serializer-deserializer (SerDes) device of the PHY, the circuitry comprises an integrator to sum the ISI values for one or more of the plurality of DFE taps, and the link loss is expected to occur based on the sum of the ISI values for the one or more of the plurality of DFE taps.
10 . The computer-readable medium of claim 9 , wherein the parameters comprise one or more of: eye height, signal to noise ratio (SNR), phase lock loop (PLL) lock range, phase alignment values, equalizer coefficients, bias currents measured by an on-die analog-to-digital (A/D) converter, offset cancellation parameters, raw bit error rate (BER) error dependence statistics, and/or counter values of corrected and uncorrected Forward Error Correction (FEC) values.
11 . The computer-readable medium of claim 9 , comprising instructions stored thereon, that if executed by one or more processors, cause the one or more processors to:
configure the circuitry to adjust an interval of parameter measurements based on the link loss being expected.
12 . The computer-readable medium of claim 9 , wherein to indicate a potential connector dislocation based on changes to the ISI data, the circuitry is configured to:
store a baseline ISI data for connector reflections;
measure ISI data for connector reflections; and
indicate a potential connector dislocation based on measured ISI data and baseline ISI data.
13 . A method comprising:
autonomously measuring, by circuitry of a physical layer interface (PHY), for signal degradation by measurement of baseline parameters and
indicating, by the circuitry of the PHY, if link loss is expected to occur based on the baseline parameters and one or more subsequent measurements of parameters, wherein the parameters comprise inter symbol interference (ISI) values measured from one or more of a plurality of decision feedback equalizer (DFE) taps of a serializer-deserializer (SerDes) device of the PHY, the circuitry comprises an integrator to sum the ISI values for one or more of the plurality of DFE taps, and the link loss is expected to occur based on the sum of the ISI values for the one or more of the plurality of DFE taps.
14 . The method of claim 13 , wherein the parameters comprise one or more of: eye height, signal to noise ratio (SNR), phase lock loop (PLL) lock range, phase alignment values, equalizer coefficients, bias currents measured by an on-die analog-to-digital (A/D) converter, offset cancellation parameters, raw bit error rate (BER) error dependence statistics, and/or counter values of corrected and uncorrected Forward Error Correction (FEC) values.
15 . The method of claim 13 , comprising:
adjusting an interval of parameter measurements based on link loss being expected.
16 . The method of claim 13 , comprising:
indicating a potential connector dislocation based on changes to ISI data.
17 . The method of claim 16 , wherein indicating a potential connector dislocation based on changes to ISI data comprises:
storing a baseline ISI data for connector reflections;
measuring ISI data for connector reflections; and
indicating a potential connector dislocation based on measured ISI data and baseline ISI data.
18 . A system comprising:
a first host system comprising a processor and a memory;
a transmitter, coupled to the first host system;
a second host system comprising a processor and a memory; and
a receiver, coupled to the second host system, wherein:
the transmitter is to transmit a signal to the receiver,
the receiver comprises:
one or more slicers to provide data and error based on the signal received by the receiver, and
a physical layer interface (PHY) comprising:
a serializer-deserializer (SerDes) device comprising a plurality of decision feedback equalizer (DFE) taps, and
circuitry, coupled to the SerDes device, configured to autonomously measure for signal degradation and to indicate if link loss is expected to occur based on a baseline measurement of parameters and one or more subsequent measurements of parameters, wherein:
the parameters comprise inter symbol interference (ISI) values measured from one or more of the plurality of DFE taps,
the circuitry comprises an integrator to sum the ISI values for one or more of the plurality of DFE taps, and
the link loss is expected to occur based on the sum of the ISI values for the one or more of the plurality of DFE taps.
19 . The system of claim 18 , wherein:
the first host system is to provide data to the transmitter for transmission in the signal to the receiver and
the receiver is to provide the data from the one or more slicers to the second host system.
20 . The system of claim 18 , wherein the parameters comprise one or more of: eye height, signal to noise ratio (SNR), phase lock loop (PLL) lock range, phase alignment values, equalizer coefficients, bias currents measured by an on-die analog-to-digital (A/D) converter, offset cancellation parameters, raw bit error rate (BER) error dependence statistics, and/or counter values of corrected and uncorrected Forward Error Correction (FEC) values.
21 . The system of claim 18 , wherein the circuitry is to indicate a potential connector dislocation based on changes to ISI data.