IP Library › Granted Patent US 12712757
Granted Patent B2
US 12712757 · App. 18/824,294 · Granted Aug 18, 2026

Fast serial data communications

Inventor: Jens Barrenscheen (Munich, DE)
Assignee: Infineon Technologies AG
H04L12/40
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12712757
App. No.
18/824,294
Granted
Aug 18, 2026
Kind
B2
Abstract

A serial communications device alternates between triggering the shifting out of an SDO bit and triggering the shifting in of an SDI bit relative a first shift clock edge and a second shift clock edge of a shift clock signal SCLK that are separated by a first time difference. The serial communication device is further configured to trigger the shifting in of the SDI bit separated from triggering the shifting out of the SDO bit by a second time difference that is longer than the first time difference.

Claims (61)

1 . A method, comprising:

alternating between triggering shifting out of a Serial Data Out (SDO) bit and triggering shifting in of a Serial Data In (SDI) bit relative to a first shift clock edge separated from a second shift clock edge of a shift clock signal SCLK by a first time difference; and

triggering the shifting in of the SDI bit separated from triggering the shifting out of the SDO bit by a second time difference that is longer than the first time difference.

2 . The method of claim 1 , further comprising:

by a peripheral node, triggering the shifting in of the SDI bit the second time difference after triggering the shifting out of the SDO bit.

3 . The method of claim 2 , wherein triggering the shifting in of the SDI bit the second time difference after triggering the shifting out of the SDO bit comprises applying, by the peripheral node, a known delay after the second shift clock edge before triggering the shifting in of the SDI bit.

4 . The method of claim 1 , further comprising:

triggering the shifting out of the SDO bit the second time difference before triggering the shifting in of the SDI bit.

5 . The method of claim 4 , wherein triggering the shifting out of the SDO bit the second time difference before triggering the shifting in of the SDI bit comprises applying a known delay after the second shift clock edge before triggering the shifting out of the SDO bit.

6 . The method of claim 1 , wherein the second time difference has a duration selected to accommodate a propagation delay.

7 . The method of claim 1 , further comprising:

triggering the shifting out of a current SDO bit at substantially the same time or immediately after triggering the shifting in of a previous SDI bit.

8 . The method of claim 1 , wherein the second time difference is substantially equal to or slightly less than a full period of the SCLK signal.

9 . The method of claim 1 , wherein the first shift clock edge and the second shift clock edge are successive edges of the shift clock signal SCLK separated by the first time difference.

10 . The method of claim 1 , further comprising:

triggering, by a peripheral node, the shifting in of the SDI bit the second time difference after triggering the shifting out of the SDO bit; and

triggering, by a host node, the shifting out of the SDO bit the second time difference before triggering the shifting in of the SDI bit.

11 . The method of claim 1 , further comprising:

triggering, by a host node, the shifting in of the SDI bit the second time difference after triggering the shifting out of the SDO bit; and

triggering, by a peripheral node, the shifting out of the SDO bit the second time difference before triggering the shifting in of the SDI bit.

12 . The method of claim 1 , further comprising:

triggering, by a peripheral node the shifting in of the SDI bit the second time difference after triggering the shifting out of the SDO bit; and

triggering, by the peripheral node, the shifting out of the SDO bit the second time difference before triggering the shifting in of the SDI bit.

13 . The method of claim 1 , further comprising:

triggering, by a host node, the shifting in of the SDI bit the second time difference after triggering the shifting out of the SDO bit; and

triggering, by the host node, the shifting out of the SDO bit the second time difference before triggering the shifting in of the SDI bit.

14 . A communications device configured to:

alternate between triggering shifting out of a Serial Data Out (SDO) bit and triggering shifting in of a Serial Data In (SDI) bit relative to a first shift clock edge separated from a second shift clock edge of a shift clock signal SCLK by a first time difference; and

trigger the shifting in of the SDI bit separated from the triggering the shifting out of the SDO bit by a second time difference that is longer than the first time difference.

15 . The communications device of claim 14 , wherein the communications device is a peripheral node configured to:

trigger the shifting in of the SDI bit the second time difference after triggering the shifting out the SDO bit.

16 . The communications device of claim 15 , wherein the peripheral node is configured to:

apply a known delay after the second shift clock edge before triggering the shifting in of the SDI bit.

17 . The communications device of claim 14 , wherein the communications device is configured to:

trigger the shifting out of the SDO bit the second time difference before triggering the shifting in of the SDI bit.

18 . The communications device of claim 17 , wherein the communications device is configured to:

apply a known delay after the second shift clock edge before triggering the shifting out of the SDO bit.

19 . The communications device of claim 14 , wherein the second time difference has a duration selected to accommodate a propagation delay.

20 . The communications device of claim 14 , wherein the communications device is configured to:

trigger the shifting out of a current SDO bit at the same time as or immediately after triggering the shifting in of a previous SDI bit.

21 . The communications device of claim 14 , wherein the second time difference is substantially equal to or slightly less than a full period of the SCLK signal.

22 . The communications device of claim 14 , wherein the first shift clock edge and the second shift clock edge are successive edges of the shift clock signal SCLK separated by the first time difference.

23 . The communications device of claim 14 , wherein the communications device is further configured to:

trigger the shifting in of the SDI bit the second time difference after triggering the shifting out of the SDO bit; and

trigger the shifting out of the SDO bit the second time difference before triggering the shifting in of the SDI bit.

24 . A system, comprising:

a host node; and

a peripheral node configured to:

alternate between triggering shifting out of a Serial Data Out (SDO) bit and triggering shifting in of a Serial Data In (SDI) bit relative to a first shift clock edge separated from a second shift clock edge by a first time difference; and

trigger the shifting in of the SDI bit separated from triggering the shifting out of the SDO bit by a second time difference that is longer than the first time difference.

25 . The system of claim 24 , wherein the host node is configured to:

alternate between triggering shifting out of an SDO bit and triggering shifting in of an SDI bit relative to the first shift clock edge separated from the second shift clock edge by the first time difference; and

trigger the shifting in of an SDI bit separated from triggering the shifting out of an SDO bit by the second time difference.

26 . The system of claim 24 , wherein one or more of the host node and the peripheral node are configured to:

trigger the shifting out of the SDO bit the second time difference before triggering the shifting in of the SDI bit.

27 . The system of claim 24 , wherein the peripheral node is configured to:

trigger the shifting in of the SDI bit the second time difference after triggering the shifting out of the SDO bit.

28 . The system of claim 24 , wherein the peripheral node is configured to trigger the shifting in of the SDI bit the second time difference after triggering the shifting out of the SDO bit, and the host node is configured to trigger the shifting out of the SDO bit the second time difference before triggering the shifting in of the SDI bit.

29 . The system of claim 24 , wherein the host node is configured to trigger the shifting in of the SDI bit the second time difference after triggering the shifting out of the SDO bit, and to trigger the shifting out of the SDO bit the second time difference before triggering the shifting in of the SDI bit.

30 . The system of claim 24 , wherein the peripheral node is configured to trigger the shifting in of the SDI bit the second time difference after triggering the shifting out of the SDO bit, and to trigger the shifting out of the SDO bit the second time difference before triggering the shifting in of the SDI bit.

31 . The system of claim 24 , wherein the peripheral node and the host node are configured to trigger the shifting in of the SDI bit the second time difference after triggering the shifting out of the SDO bit, and to trigger the shifting out of the SDO bit the second time difference before triggering the shifting in of the SDI bit.