Data and clock transmission over a magnetic channel

1 . A circuit, comprising:

a transformer including a primary coil and a secondary coil;

an excitation driver circuit having a driver input and a driver output, wherein the driver output is coupled to the primary coil;

a clock circuit having a clock output coupled to the driver input;

a clock detection circuit having a detection input and a detection output, wherein the detection input is coupled to the secondary coil;

a data interface circuit having a clock input, a data input and an interface output, the clock input coupled to the detection output; and

a circuit coupled between the interface output and the secondary coil, the load circuit including a modulation input coupled to the interface output.

2 . The circuit of claim 1 , wherein the driver output includes first and second excitation outputs, wherein the first excitation output is coupled to a first primary terminal of the primary coil and the second excitation output is coupled to a second primary terminal of the primary coil.

3 . The circuit of claim 2 , further including a data detection circuit that includes a data output resistor having a first resistor terminal and a second resistor terminal, in which the first resistor terminal is coupled to the first excitation output, and the second resistor terminal is coupled to the first primary terminal.

4 . The circuit of claim 3 , wherein the data detection circuit further includes a data output circuit having a first data input terminal, a second data input terminal and a data output terminal, in which the first data input terminal is coupled to the first resistor terminal of the data output resistor, and the second data input terminal is coupled to the second resistor terminal of the data output resistor.

5 . The circuit of claim 2 , further including a primary-side data driver circuit having a first driver output terminal and a second driver output terminal,

the first driver output terminal is coupled to the first primary terminal of the primary coil, and

the second driver output terminal is coupled to the second primary terminal of the primary coil.

6 . The circuit of claim 1 , wherein the detection input includes a first detection input and a second detection input, wherein the first detection input is coupled to a first secondary terminal of the secondary coil and the second detection input is coupled to a second secondary terminal of the secondary coil.

7 . The circuit of claim 6 , wherein the data input of the data interface circuit is coupled to a data input circuit.

8 . The circuit of claim 6 , wherein the circuit includes:

a capacitor having a first capacitor terminal and a second capacitor terminal; and

a switch having a first switch terminal, a second switch terminal and the modulation input,

wherein the first capacitor terminal is coupled to the first secondary terminal of the secondary coil, the second capacitor terminal is coupled to the first switch terminal of the switch, the second switch terminal of the switch is coupled to the second secondary terminal of the secondary coil, and the modulation input of the switch is coupled to the interface output.

9 . The circuit of claim 1 , wherein excitation driver circuit is configurable to provide an excitation signal at the driver output and the clock detection circuit is configurable to provide a detected clock signal at the detection output based on a secondary voltage across the secondary coil responsive to the excitation signal.

10 . The circuit of claim 9 , wherein the excitation signal and the detected clock signal are at a clock frequency.

11 . The circuit of claim 8 , wherein the data interface circuit is configurable to provide a secondary data signal at the interface output based on the detected clock signal at the clock input and input data received at the data input.

12 . The circuit of claim 10 , wherein the circuit is configurable to modulate an impedance across the secondary coil responsibe to receiving the secondary data signal at the modulation input form the interface output.

13 . A system comprising:

a transformer including a primary coil and a secondary coil;

an excitation driver circuit having a driver input and a driver output, the driver output being coupled to the primary coil, wherein the excitation driver circuit is configurable to provide an excitation signal at a clock frequency at the driver output;

a clock circuit having a clock output coupled to the driver input and configurable to provide a clock signal at the clock frequency at the clock output;

a clock detection circuit having a detection input and a detection output, the detection input being coupled to the secondary coil, wherein the clock detection circuit is configurable to provide a detected clock signal at the clock frequency at the detection output based on a secondary voltage across the secondary coil responsive to the excitation signal;

a data interface circuit having a clock input, a data input and an interface output, the clock input being coupled to the detection output, wherein the data interface circuit is configurable to provide a secondary data signal at the interface output based on the detected clock signal and input data at the data input; and

a circuit coupled between the interface output and the secondary coil, the circuit including a modulation input coupled to the interface output, wherein the circuit is configurable to modulate an impedance across the secondary coil responsive to the secondary data signal.

14 . The system of claim 13 , further including a data detection circuit configurable to detect the secondary data signal based on a primary input impedance induced across the primary coil responsive to the modulated impedance.