Low-power analog decision feedback equalizer
A communications circuit includes a receiver (RX) frontend coupled to an RX deserializer and the RX frontend includes a decision feedback equalizer coupled directly between an output and an input of the RX frontend. The decision feedback equalizer may include a first inverter and a series combination of a first resistor and a first capacitor coupled in series with the first inverter.
1 . A communications circuit comprising:
a receiver (RX) frontend coupled to an RX deserializer;
wherein the RX frontend comprises a decision feedback equalizer coupled directly between an output and an input of the RX frontend, the decision feedback equalizer comprising:
a first inverter; and
a series combination of a first resistor and a first capacitor coupled in series with the first inverter, wherein the series combination of the first resistor and the first capacitor combined with an input resistor of the RX frontend operates as a bandpass filter configured to coincide with a first post cursor output by the RX frontend.
2 . The communications circuit of claim 1 , wherein a capacitance of the first capacitor and a resistance of the first resistor are selected based on a feedback delay and channel characteristics of the RX frontend.
3 . The communications circuit of claim 1 , wherein a data rate supported by the RX frontend is higher than 32 gigabits per second.
4 . The communications circuit of claim 1 , wherein the RX frontend and the RX deserializer are configured to operate at a supply voltage that is lower than 1.0 volt.
5 . The communications circuit of claim 1 , wherein:
the first inverter is coupled to a positive output of the RX frontend;
the series combination of the first resistor and first capacitor is coupled to a positive differential tap point of the input of the RX frontend; and
the decision feedback equalizer further comprises:
a second inverter coupled to a negative output of the RX frontend; and
a second series combination of a second resistor and a second capacitor coupled in series with the second inverter and to a negative differential tap point of the input of the RX frontend.
6 . The communications circuit of claim 5 , wherein a resistance of the first and second resistors is matched within first device tolerances, and a capacitance of the first and second capacitors is approximately matched within second device tolerances.
7 . The communications circuit of claim 5 , wherein the RX frontend further comprises a single-to-differential signal amplifier comprising both the positive differential tap point and the negative differential tap point.
8 . A communications device comprising:
a receiver (RX) frontend coupled to an RX deserializer, wherein the RX frontend comprises:
a single-to-differential signal amplifier;
a trans-admittance stage (TAS) coupled to the single-to-differential signal amplifier;
a trans-impedance amplifier (TIA) coupled to the TAS; and
a decision feedback equalizer coupled directly between an output of the TIA and an input to the single-to-differential signal amplifier, wherein the decision feedback equalizer comprises:
a first inverter coupled to a positive output of the TIA; and
a series combination of a first resistor and a first capacitor coupled in series with the first inverter and to a positive differential tap point of the input to the single-to-differential signal amplifier.
9 . The communications device of claim 8 , wherein the series combination of the first resistor and the first capacitor is combined with an input resistor of the single-to-differential signal amplifier and operates as a bandpass filter configured to coincide with a first post cursor output by the TIA.
10 . The communications device of claim 9 , wherein a capacitance of the first capacitor and a resistance of the first resistor are selected based on a feedback delay and channel characteristics of the RX frontend.
11 . The communications device of claim 8 , wherein a data rate supported by the RX frontend is higher than 32 gigabits per second.
12 . The communications device of claim 8 , wherein the RX frontend and the RX deserializer are configured to operate at a supply voltage that is lower than 1.0 volt.
13 . The communications device of claim 8 , wherein the decision feedback equalizer further comprises:
a second inverter coupled to a negative output of the TIA; and
a series combination of a second resistor and a second capacitor coupled in series with the second inverter and to a negative differential tap point of the input to the single-to-differential signal amplifier.
14 . The communications device of claim 13 , wherein a resistance of the first and second resistors is matched within first device tolerances, and a capacitance of the first and second capacitors is approximately matched within second device tolerances.
15 . The communications device of claim 13 , wherein:
the positive differential tap point is located in a first source of a first n-type metal-oxide semiconductor (NMOS) transistor, which is positioned in a positive side of the single-to-differential signal amplifier; and
the negative differential tap point is located in a second source of a second NMOS transistor, which is positioned in a negative side of the single-to-differential signal amplifier.
16 . A method of operating a communications circuit comprising a receiver (RX) frontend including an analog decision feedback equalizer coupled to an RX deserializer, wherein the method comprises:
coupling a first feedback loop of the analog decision feedback equalizer directly between a positive output of the RX frontend to a positive differential tap point of an input to a single-to-differential amplifier of the RX frontend; and
coupling a second feedback loop of the analog decision feedback equalizer directly between a negative output of the RX frontend to a negative differential tap point of the input to the single-to-differential amplifier of the RX frontend.
17 . The method of claim 16 , wherein the first feedback loop comprises a first inverter and a series combination of a first resistor and a first capacitor coupled in series with the first inverter, and wherein the analog decision feedback equalizer does not sample the positive output of the RX frontend.
18 . The method of claim 16 , wherein the second feedback loop comprises a second inverter and a series combination of a second resistor and a second capacitor coupled in series with the second inverter, and wherein the analog decision feedback equalizer does not sample the negative output of the RX frontend.
19 . The method of claim 18 , further comprising designing the series combination of the second resistor and the second capacitor combined with an input resistor of the single-to-differential amplifier of the RX frontend as a bandpass filter configured to coincide with a first post cursor output by the RX frontend.