Asynchronous non-orthogonal multiple access for ambient internet of things (AIoT) devices
Various aspects of the present disclosure relate to performing non-orthogonal multiple access (NOMA) for ambient Internet of Things (AIoT) devices. For example, each AIoT device of a group of AIoT devices (e.g., a group of AIoT devices associated with a reader device) may append to transmitted data a prefix at the start of one or more chips with the transmitted data. An associated network entity may determine a length or duration of the prefix (or prefixes). In doing so, the NOMA mechanism enables the AIoT devices to utilize NOMA when transmitting data.
1 . A user equipment (UE) for wireless communication, comprising:
at least one memory; and
at least one processor coupled with the at least one memory and configured to cause the UE to:
determine one or more groups of chips for transmission over a physical device-to-reader channel (PDRCH),
wherein the transmission comprises a preamble and a postamble, and
wherein the one or more groups of chips for transmission over the PDRCH are located between the preamble and the postamble;
append a prefix to each group of chips of the one or more groups of chips,
wherein the prefix is appended to a beginning chip of each group of chips; and
perform the transmission on the PDRCH over one or more non-orthogonal resources.
2 . The UE of claim 1 , wherein the at least one processor is configured to cause the UE to perform the transmission on the PDRCH over the one or more non-orthogonal resources to a network entity or a reader device.
3 . The UE of claim 1 , wherein each group of chips comprises a quantity of chips, and wherein the quantity of chips is based at least in part on a configuration.
4 . The UE of claim 3 , where the configuration is based on a length of the PDRCH, variations of a sampling frequency offset (SFO) over time at the UE, variations of a carrier frequency offset (CFO) over time at the UE, or combinations thereof.
5 . The UE of claim 1 , wherein the at least one processor is configured to cause the UE to receive signaling that indicates a configuration from a network entity or a reader device, wherein the signaling comprises a medium access control-control element (MAC-CE).
6 . The UE of claim 1 , wherein the at least one processor is configured to cause the UE to:
receive an indication of an orthogonal sequence,
wherein the prefix comprises the orthogonal sequence, and
wherein the orthogonal sequence is associated with auto-correlation properties or cross-correlation properties satisfying a criterion.
7 . The UE of claim 1 , wherein a length of the prefix is based on a highest timing error caused by a sampling frequency offset (SFO) associated with another UE of a group of UEs, including the UE, that share the one or more non-orthogonal resources.
8 . The UE of claim 1 , wherein the at least one processor is configured to cause the UE to:
receive a configuration that identifies a certain delay of transmission based on a size of the PDRCH; and
perform the transmission on the PDRCH after the certain delay.
9 . The UE of claim 1 , wherein the UE is an ambient Internet of Things (AIoT) device.
10 . The UE of claim 1 , wherein the UE is a passive AIoT device, a semi-passive AIoT device, or an active AIoT device.
11 . A processor for wireless communication, comprising:
at least one controller coupled with the at least one memory and configured to cause the processor to:
determine one or more groups of chips for transmission over a physical device-to-reader channel (PDRCH),
wherein the transmission comprises a preamble and a postamble, and
wherein the one or more groups of chips for transmission over the PDRCH are located between the preamble and the postamble;
append a prefix to each group of chips of the one or more groups of chips,
wherein the prefix is appended to a beginning chip of each group of chips; and
perform the transmission on the PDRCH over non-orthogonal resources.
12 . The processor of claim 11 , wherein each group of chips comprises a quantity of chips, and wherein the quantity of chips is based at least in part on a configuration.