IP Library › Granted Patent US 12712797

Granted Patent B2

US 12712797 · App. 18/382,215 · Granted Aug 18, 2026

Method and apparatus for determining time of flight

Inventors: Shaoan Dai (San Jose, CA); Wensheng Sun (Newark, CA); Xing Wu (Palo Alto, CA); Zhenzhong Gu (San Jose, CA)

Assignee: Marvell Asia Pte Ltd

H04L43/106 H04B1/16 H04B1/3822 H04L7/033 H04L7/0337 H04L7/044 H04L12/12 H04L41/12 H04J3/0685 H04L7/0079 H04L7/0091

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Quick Facts

Patent No.: US 12712797
App. No.: 18/382,215
Granted: Aug 18, 2026
Kind: B2

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USPTO Patent Center↗ Full Patent PDF↗

Abstract

A first communication device receives an analog receive signal via a communication medium. An ADC of the first communication device converts the analog receive signal to a digital receive signal. Logic circuitry of the first communication device detects a plurality of timing signals from a second communication device based on analyzing the digital receive signal. The logic circuitry adjusts a sampling phase of the ADC in connection with at least some of the timing signals so that the ADC is using different sampling phases when different ones of the timing signals are detected. The logic circuitry determines timing information based on the detection of the plurality of timing signals when the ADC is using different sampling phases when different ones of the timing signals are detected. The first communication device determines a time of flight between the first communication device and the second communication device based on the timing information.

Claims (83)

1 . A transceiver associated with a first communication device, comprising:

an analog-to-digital converter (ADC) configured to generate a digital receive signal based on an analog receive signal received via a communication medium;

timing signal detection circuitry coupled to the ADC, the timing signal detection circuitry configured to detect a plurality of timing signals from a second communication device during a time of flight measurement procedure based on analyzing the digital receive signal;

sampling phase generation circuitry configured to adjust a sampling phase used by the ADC in connection with at least some of the timing signals so that the ADC is using different sampling phases when different ones of the timing signals are detected;

a switch configured to i) couple an output of the sampling phase generation circuitry to the ADC during the time of flight measurement procedure, and ii) couple a phase control output of receive circuitry to the ADC during normal operation of the transceiver;

timing information determination circuitry configured to determine timing information based on the detection of the plurality of timing signals when the ADC is using different sampling phases when different ones of the timing signals are detected; and

a processor configured to determine the time of flight based on the timing information.

2 . The transceiver of claim 1 , wherein the sampling phase generation circuitry is configured to adjust the sampling phase in connection with detecting each of the at least some of the timing signals.

3 . The transceiver of claim 2 , wherein the sampling phase generation circuitry is configured to adjust the sampling phase in response to detecting each of the at least some of the timing signals.

4 . The transceiver of claim 1 , wherein:

the timing information determination circuitry comprises a counter configured to count timing signals detected by the timing signal detection circuitry; and

the processor is configured to:

determine a time period until a number of timing signals are detected, and

determine the time of flight based on i) the number of timing signals, and ii) the time period.

5 . The transceiver of claim 4 , wherein the counter is a first counter, and wherein:

the processor comprises a second counter configured to count a number of cycles of a clock until the number of timing signals is detected, the number of cycles of the clock indicating the time period; and

the processor is configured to determine the time of flight based on i) the number of timing signals, and ii) the number of cycles of the clock.

6 . The transceiver of claim 1 , wherein the timing signals are reverse timing signals, and wherein the transceiver further comprises transmit circuitry that is configured to:

generate an analog transmit signal that includes a plurality of forward timing signals; and

transmit the analog transmit signal via the communication medium, wherein each forward timing signal prompts the second communication device to transmit a respective reverse timing signal.

7 . A method for measuring a time of flight between a first communication device and a second communication device, the method comprising:

receiving, at the first communication device, an analog receive signal via a communication medium;

converting, at an analog-to-digital converter (ADC) of the first communication device, the analog receive signal to a digital receive signal;

detecting, at logic circuitry of the first communication device, a plurality of timing signals from the second communication device during a time of flight measurement procedure based on analyzing the digital receive signal;

coupling, with a switch, an output of a phase generator to the ADC during the time of flight measurement procedure;

coupling, with the switch, a phase control output of a receiver to the ADC during normal operation;

adjusting, with the phase generator, a sampling phase of the ADC in connection with at least some of the timing signals so that the ADC is using different sampling phases when different ones of the timing signals are detected during the time of flight measurement procedure;

determining, at the logic circuitry, timing information based on the detection of the plurality of timing signals when the ADC is using different sampling phases when different ones of the timing signals are detected; and

determining, at the first communication device, the time of flight based on the timing information.

8 . The method of claim 7 , wherein adjusting the sampling phase of the ADC comprises adjusting the sampling phase in connection with detecting each of the at least some of the timing signals.

9 . The method of claim 8 , wherein adjusting the sampling phase in connection with detecting each of the at least some of the timing signals comprises adjusting the sampling phase in response to detecting each of the at least some of the timing signals.

10 . The method of claim 7 , wherein:

determining the timing information comprises:

counting, at the logic circuitry, timing signals detected by the logic circuitry, and

determining, at the first communication device, a time period until a number of timing signals are detected; and

determining the time of flight comprises determining the time of flight based on i) the number of timing signals, and ii) the time period.

11 . The method of claim 10 , wherein:

determining the time period comprises counting a number of cycles of a clock until the number of timing signals is detected; and

determining the time of flight comprises determining the time of flight based on i) the number of timing signals, and ii) the number of cycles of the clock.

12 . The method of claim 7 , wherein the timing signals are reverse timing signals, and wherein the method further comprises:

generating, at the first communication device, an analog transmit signal that includes a plurality of forward timing signals;

13 . A transceiver associated with a first communication device, comprising:

forward signal generation circuitry configured to generate a digital transmit signal that includes a plurality of forward timing signals;

a digital to analog converter (DAC) configured to generate an analog transmit signal based on the digital transmit signal;

clock phase adjustment circuitry configured to adjust a phase of a clock provided to the DAC in connection with at least some of the forward timing signals so that the DAC is using different phases of the clock when different ones of the forward timing signals are transmitted;

driver circuitry configured to transmit the analog transmit signal via the communication medium, wherein each forward timing signal prompts the second communication device to transmit a respective reverse timing signal, and wherein the use by the DAC of the different phases of the clock when different ones of the forward timing signals are transmitted affects timing of respective transmissions of respective ones of the reverse timing signals;

an analog-to-digital converter (ADC) configured to generate a digital receive signal based on an analog receive signal received via the communication medium;

timing signal detection circuitry coupled to the ADC, the timing signal detection circuitry configured to detect a plurality of reverse timing signals from the second communication device based on analyzing the digital receive signal;

timing information determination circuitry configured to determine timing information based on the detection of the plurality of reverse timing signals; and

a processor configured to determine the time of flight based on the timing information.

14 . The transceiver of claim 13 , wherein the clock phase adjustment circuitry is configured to adjust the clock phase in connection with the transceiver transmitting each of the at least some of the forward timing signals.

15 . The transceiver of claim 14 , wherein the clock phase adjustment circuitry is configured to adjust the clock phase in response to the transceiver transmitting each of the at least some of the forward timing signals.

16 . The transceiver of claim 13 , wherein the clock phase adjustment circuitry is configured to adjust the clock phase in connection with the timing signal detection circuitry detecting each of at least some of the reverse timing signals.

17 . The transceiver of claim 16 , wherein the clock phase adjustment circuitry is configured to adjust the phase of the clock in response to the timing signal detection circuitry detecting each of at least some of the reverse timing signals.

18 . The transceiver of claim 13 , wherein:

the timing information determination circuitry comprises a counter configured to count reverse timing signals detected by the timing signal detection circuitry; and

the processor is configured to:

determine a time period until a number of reverse timing signals are detected, and

determine the time of flight based on i) the number of reverse timing signals, and ii) the time period.

19 . The transceiver of claim 18 , wherein the counter is a first counter, and wherein:

the processor comprises a second counter configured to count a number of cycles of the clock until the number of reverse timing signals is detected, the number of cycles of the clock indicating the time period; and

the processor is configured to determine the time of flight based on i) the number of reverse timing signals, and ii) the number of cycles of the clock.

20 . A method for measuring a time of a flight between a first communication device and a second communication device, the method comprising:

generating, at the first communication device, a digital transmit signal that includes a plurality of forward timing signals;

generating, at a digital to analog converter (DAC) of the first communication device, an analog transmit signal based on the digital transmit signal;

adjusting, at logic circuitry of the first communication device, a phase of a clock provided to the DAC in connection with at least some of the forward timing signals so that the DAC is using different phases of the clock when different ones of the forward timing signals are transmitted;

transmitting, by the first communication device, the analog transmit signal via the communication medium, wherein each forward timing signal prompts the second communication device to transmit a respective reverse timing signal, and wherein the use by the DAC of the different phases of the clock when different ones of the forward timing signals are transmitted affects timing of respective transmissions of respective ones of the reverse timing signals;

receiving, at the first communication device, an analog receive signal via the communication medium;

converting, at an analog-to-digital converter (ADC) of the first communication device, the analog receive signal to a digital receive signal;

detecting, at the logic circuitry, a plurality of reverse timing signals from the second communication device based on analyzing the digital receive signal;

determining, at the logic circuitry, timing information based on the detection of the plurality of reverse timing signals; and

determining, at the first communication device, the time of flight based on the timing information.

21 . The method of claim 20 , wherein adjusting the phase of the clock provided to the DAC comprises adjusting the phase of the clock in connection with transmitting each of the at least some of the forward timing signals.

22 . The method of claim 21 , wherein adjusting the phase of the clock provided to the DAC comprises adjusting the phase of the clock in response to transmitting each of the at least some of the forward timing signals.

23 . The method of claim 20 , wherein:

determining the timing information comprises:

counting, at the logic circuitry, reverse timing signals detected by the logic circuitry, and

determining, at the first communication device, a time period until a number of reverse timing signals are detected; and

determining the time of flight comprises determining the time of flight based on i) the number of reverse timing signals, and ii) the time period.

24 . The method of claim 23 , wherein:

determining the time period comprises counting a number of cycles of the clock until the number of reverse timing signals is detected; and

determining the time of flight comprises determining the time of flight based on i) the number of reverse timing signals, and ii) the number of cycles of the clock.