Packet processor memory reservation
A network device may include packet processor memory circuitry and processing circuitry coupled to the packet processor memory circuitry. The processing circuitry may receive a set of network traffic processing features for which data is to be stored in the packet processor memory and may receive memory reservation parameters for the set of network traffic processing features. Based on the received information, the processing circuitry may obtain and maintain memory reservation layout information for the set of features.
1 . A network device comprising:
memory circuitry including a packet processor memory;
a packet processor coupled to the packet processor memory and configured to process network traffic using the packet processor memory; and
processing circuitry coupled to the memory circuitry and configured to:
receive a plurality of network traffic processing features for which data is to be stored in the packet processor memory, the plurality of network traffic processing features including at least first and second network traffic processing features;
obtain memory reservation parameters for the plurality of network traffic processing features;
generate a memory reservation layout identifying memory portions of the packet processor memory to be reserved for the plurality of network traffic processing features based on the received memory reservation parameters, wherein at least a first memory portion, of the memory portions, to be reserved for the first network traffic processing feature includes one or more memory slices having a first width and wherein at least a second memory portion, of the memory portions, to be reserved for the second network traffic processing feature includes horizontally chained memory slices having a second width greater than the first width; and
store the memory reservation layout in the memory circuitry.
2 . The network device defined in claim 1 , wherein the packet processor memory is a ternary content addressable memory having a plurality of memory slices, including the one or more memory slices and the horizontally chained memory slices, and wherein each memory slice of the plurality of memory slices has a unit width along a first dimension and a unit depth along a second dimension.
3 . The network device defined in claim 2 , wherein the horizontally chained memory slices are adjacent to each other along the first dimension.
4 . The network device defined in claim 1 , wherein the memory reservation parameters comprise an indication of feature entry width for each network traffic processing feature in the plurality of network traffic processing features.
5 . The network device defined in claim 4 , wherein the indication of feature entry width is based on one or more key fields associated with each network traffic processing feature in the plurality of network traffic processing features.
6 . The network device defined in claim 4 , wherein the memory reservation parameters comprise an indication of a number of entries for each network traffic processing feature in the plurality of network traffic processing features.
7 . The network device defined in claim 6 , wherein the processing circuitry is configured to determine a scale for each network traffic processing feature in the plurality of network traffic processing features based on the indication of feature entry width and the indication of the number of entries.
8 . The network device defined in claim 7 , wherein the processing circuitry is configured to determine a feasibility of reserving memory in the packet processor memory for the plurality of network traffic processing features using a combined scale of the plurality of network traffic processing features based on the scale for each network traffic processing feature in the plurality of network traffic processing features.
9 . The network device defined in claim 4 , wherein the processing circuitry is configured to determine the memory portions of the packet processor memory to be reserved for the plurality of network traffic processing features by reserving the memory portions for the plurality of network traffic processing features in an order based on feature entry width as determined by the indication of feature entry width.
10 . The network device defined in claim 4 , wherein the memory reservation parameters comprise an indication of priority for each network traffic processing feature in the plurality of network traffic processing features.
11 . The network device defined in claim 10 , wherein the processing circuitry is configured to determine the memory portions of the packet processor memory to be reserved for the plurality of network traffic processing features by reserving the memory portions for the plurality of network traffic processing features in an order based on feature entry width as determined by the indication of feature entry width and based on feature priority as determined by the indication of priority.
12 . The network device defined in claim 1 , wherein the plurality of network traffic processing features comprise an access control list policy feature, a quality-of-service policy feature, or a policy-based routing feature.
13 . The network device defined in claim 1 , wherein the packet processor and the packet processor memory are integrated in an integrated circuit die package.
14 . A network device comprising:
memory circuitry including a ternary content addressable memory (TCAM);
a packet processor coupled to the TCAM and configured to process network traffic using the TCAM; and
processing circuitry coupled to the memory circuitry and configured to:
receive input containing network traffic processing features and memory reservation parameters associated with the network traffic processing features, the network traffic processing features including at least first and second network traffic processing features;
generate a memory reservation layout on the TCAM for the network traffic processing features based on the received input, wherein the memory reservation layout is generated by allocating a first portion of the TCAM for the first network traffic processing feature prior to allocating a second portion of the TCAM for the second network traffic processing feature based on the first network traffic processing feature having a greater feature entry width than the second network traffic processing feature and wherein the first portion of the TCAM allocated for the first network traffic processing feature includes horizontally chained memory slices; and
provide output based on the memory reservation layout, the output identifying one or more memory slices of the TCAM reserved for use by a given network traffic processing feature in the network traffic processing features.
15 . The network device defined in claim 14 , wherein the output comprises an indication to confirm use of the memory reservation layout on the TCAM for the network traffic processing features.
16 . The network device defined in claim 14 , wherein the processing circuitry is configured to receive the input and provide the output via a command line interface.
17 . A network device comprising:
memory circuitry including a ternary content addressable memory (TCAM);
a packet processor coupled to the TCAM and configured to process network traffic using the TCAM; and
processing circuitry coupled to the memory circuitry and configured to:
receive, from device management equipment, a plurality of network traffic processing features for which data is to be stored in the TCAM, the plurality of network traffic processing features including at least first and second network traffic processing features;
obtain memory reservation parameters for the plurality of network traffic processing features;
determine a combined scale of the plurality of network traffic processing features based at least in part on the memory reservation parameters;
determine whether a memory reservation layout that includes a reserved memory portion on the TCAM for each network traffic processing feature in the plurality of network traffic processing features can be generated based on the combined scale of the plurality of network traffic processing features, wherein the memory reservation layout includes one or more memory slices to be reserved for the first network traffic processing feature and includes horizontally chained memory slices to be reserved for the second network traffic processing feature, wherein the one or more memory slices to be reserved for the first network traffic processing feature has a first width, and wherein the horizontally chained memory slices to be reserved for the second network traffic processing feature has a second width greater than the first width; and
provide output based on the determination of whether the memory reservation layout can be generated.
18 . The network device defined in claim 17 , wherein the processing circuitry is configured to determine whether the memory reservation layout can be generated at least in part by determining whether the TCAM contains at least an amount of memory space that can accommodate the combined scale of the plurality of network traffic processing features.
19 . The network device defined in claim 17 , wherein the processing circuitry is configured to:
in response to determining that the memory reservation layout cannot be generated, obtain a new plurality of network traffic processing features or a new memory reservation parameter for a given network traffic processing feature of the plurality of network traffic processing features; and
generate the memory reservation layout based on the new plurality of network traffic processing features or the new memory reservation parameter.
20 . The network device defined in claim 17 , wherein the processing circuitry is configured to:
in response to determining that the memory reservation layout cannot be generated, output a request for a new plurality of network traffic processing features or a new memory reservation parameter for a given network traffic processing feature of the plurality of network traffic processing features.