FIFO bank selection

1 . A method comprising:

at a current clock cycle, receiving a request for storing a set of first-in-first-out (FIFO) buffer data portions in a FIFO buffer implemented with a plurality of memory banks, wherein the plurality of memory banks includes a plurality of sets of memory entries; wherein each memory bank in the plurality of memory banks includes a respective set of memory entries in the plurality of sets of multiple memory entries;

in response to the request for storing the set of FIFO buffer data portions, applying one or more memory bank selection methods to select, from among the plurality of memory banks, a set of memory banks ordered in a first sequential order;

determining whether the set of memory banks as ordered in the first sequential order starts with a first memory bank identical to a last memory bank written in a last clock cycle, wherein the last clock cycle immediately precedes the current clock cycle, wherein a last sequential order used to order a last set of memory banks selected for a last set of writes in the last clock cycle ends with the last memory bank;

in response to determining that the set of memory banks as ordered in the first sequential order starts with the first memory bank identical to the last memory bank written in the last clock cycle, performing:

swapping the first memory bank with a second memory bank immediately following the first memory bank in the first sequential order to generate a second sequential order for the set of memory banks;

performing a set of writes to store the plurality of FIFO buffer data portions into the set of memory banks in accordance with the second sequential order.

2 . The method of claim 1 , further comprising: generating a bit vector corresponding to the first sequential order along with a swap bit set to indicate that a swapping operation is performed to generate the second sequential order from the first sequential order.

3 . The method of claim 2 , further comprising:

at one or more subsequent clock cycles after the current clock cycle, receiving a request for retrieving the set of FIFO buffer data portions in the FIFO buffer implemented with the plurality of memory banks;

accessing the bit vector and a swap bit to determine whether the swap bit indicates that the swapping operation has been performed to generate the second sequential order from the first sequential order, wherein the first sequential order is indicated with the bit vector;

in response to determining that the swap bit indicates that the swapping operation has been performed to generate the second sequential order from the first sequential order, perform a set of reads to retrieve the set of FIFO buffer data portions from the set of memory banks in accordance with the second sequential order.

4 . The method of claim 1 , further comprising: generating a bit vector corresponding to the first sequential order along with a swapping bit set to indicate that a swapping operation is performed to generate the second sequential order from the first sequential order.

5 . The method of claim 1 , wherein each write in the set of writes stores a respective in the set of FIFO buffer data portions into a respective memory bank in the set of memory banks.

6 . The method of claim 1 , wherein a set of reads is performed in the current clock cycle to retrieve FIFO buffer data portions from a second set of memory banks in the plurality of memory banks, wherein the one or more memory bank selection methods excludes each and every memory bank in the second set of memory banks from being selected into the set of memory banks used to perform the set of writes in the current clock cycle.

7 . The method of claim 1 , further comprising:

at a second current clock cycle, receiving a second request for storing a second set of FIFO buffer data portions in the FIFO buffer implemented with the plurality of memory banks;

in response to the second request for storing the second set of FIFO buffer data portions, applying the one or more memory bank selection methods to select, from among the plurality of memory banks, a second set of memory banks ordered in a third sequential order;

determining whether the second set of memory banks as ordered in the third sequential order starts with a third memory bank identical to a previous memory bank written in a previous clock cycle, wherein the previous clock cycle immediately precedes the second current clock cycle, wherein a previous sequential order used to order a previous set of memory banks selected for a previous set of writes in the previous clock cycle ends with the previous memory bank;

in response to determining that the second set of memory banks as ordered in the third sequential order starts with the third memory bank not identical to the previous memory bank written in the previous clock cycle, performing a second set of writes to store the second set of FIFO buffer data portions into the second set of memory banks in accordance with the third sequential order.

8 . A system comprising:

one or more computing devices;

one or more non-transitory computer readable media storing instructions that, when executed by the one or more computing devices, cause performance of:

at a current clock cycle, receiving a request for storing a set of first-in-first-out (FIFO) buffer data portions in a FIFO buffer implemented with a plurality of memory banks, wherein the plurality of memory banks includes a plurality of sets of memory entries; wherein each memory bank in the plurality of memory banks includes a respective set of memory entries in the plurality of sets of multiple memory entries;

in response to the request for storing the set of FIFO buffer data portions, applying one or more memory bank selection methods to select, from among the plurality of memory banks, a set of memory banks ordered in a first sequential order;

determining whether the set of memory banks as ordered in the first sequential order starts with a first memory bank identical to a last memory bank written in a last clock cycle, wherein the last clock cycle immediately precedes the current clock cycle, wherein a last sequential order used to order a last set of memory banks selected for a last set of writes in the last clock cycle ends with the last memory bank;

in response to determining that the set of memory banks as ordered in the first sequential order starts with the first memory bank identical to the last memory bank written in the last clock cycle, performing:

swapping the first memory bank with a second memory bank immediately following the first memory bank in the first sequential order to generate a second sequential order for the set of memory banks;

performing a set of writes to store the plurality of FIFO buffer data portions into the set of memory banks in accordance with the second sequential order.

9 . The system of claim 8 , wherein the one or more non-transitory computer readable media storing instructions that, when executed by the one or more computing devices, cause further performance of: generating a bit vector corresponding to the first sequential order along with a swap bit set to indicate that a swapping operation is performed to generate the second sequential order from the first sequential order.

10 . The system of claim 9 , wherein the one or more non-transitory computer readable media storing instructions that, when executed by the one or more computing devices, cause further performance of:

at one or more subsequent clock cycles after the current clock cycle, receiving a request for retrieving the set of FIFO buffer data portions in the FIFO buffer implemented with the plurality of memory banks;

accessing the bit vector and a swap bit to determine whether the swap bit indicates that the swapping operation has been performed to generate the second sequential order from the first sequential order, wherein the first sequential order is indicated with the bit vector;

in response to determining that the swap bit indicates that the swapping operation has been performed to generate the second sequential order from the first sequential order, perform a set of reads to retrieve the set of FIFO buffer data portions from the set of memory banks in accordance with the second sequential order.

11 . The system of claim 8 , wherein the one or more non-transitory computer readable media storing instructions that, when executed by the one or more computing devices, cause further performance of: generating a bit vector corresponding to the first sequential order along with a swapping bit set to indicate that a swapping operation is performed to generate the second sequential order from the first sequential order.

12 . The system of claim 8 , wherein each write in the set of writes stores a respective in the set of FIFO buffer data portions into a respective memory bank in the set of memory banks.

13 . The system of claim 8 , wherein a set of reads is performed in the current clock cycle to retrieve FIFO buffer data portions from a second set of memory banks in the plurality of memory banks, wherein the one or more memory bank selection methods excludes each and every memory bank in the second set of memory banks from being selected into the set of memory banks used to perform the set of writes in the current clock cycle.

14 . The system of claim 8 , wherein the one or more non-transitory computer readable media storing instructions that, when executed by the one or more computing devices, cause further performance of:

at a second current clock cycle, receiving a second request for storing a second set of FIFO buffer data portions in the FIFO buffer implemented with the plurality of memory banks;

in response to the second request for storing the second set of FIFO buffer data portions, applying the one or more memory bank selection methods to select, from among the plurality of memory banks, a second set of memory banks ordered in a third sequential order;

determining whether the second set of memory banks as ordered in the third sequential order starts with a third memory bank identical to a previous memory bank written in a previous clock cycle, wherein the previous clock cycle immediately precedes the second current clock cycle, wherein a previous sequential order used to order a previous set of memory banks selected for a previous set of writes in the previous clock cycle ends with the previous memory bank;

in response to determining that the second set of memory banks as ordered in the third sequential order starts with the third memory bank not identical to the previous memory bank written in the previous clock cycle, performing a second set of writes to store the second set of FIFO buffer data portions into the second set of memory banks in accordance with the third sequential order.

15 . One or more non-transitory computer readable media storing instructions that, when executed by one or more computing devices, cause performance of:

at a current clock cycle, receiving a request for storing a set of first-in-first-out (FIFO) buffer data portions in a FIFO buffer implemented with a plurality of memory banks, wherein the plurality of memory banks includes a plurality of sets of memory entries; wherein each memory bank in the plurality of memory banks includes a respective set of memory entries in the plurality of sets of multiple memory entries;

in response to the request for storing the set of FIFO buffer data portions, applying one or more memory bank selection methods to select, from among the plurality of memory banks, a set of memory banks ordered in a first sequential order;

determining whether the set of memory banks as ordered in the first sequential order starts with a first memory bank identical to a last memory bank written in a last clock cycle, wherein the last clock cycle immediately precedes the current clock cycle, wherein a last sequential order used to order a last set of memory banks selected for a last set of writes in the last clock cycle ends with the last memory bank;

in response to determining that the set of memory banks as ordered in the first sequential order starts with the first memory bank identical to the last memory bank written in the last clock cycle, performing:

swapping the first memory bank with a second memory bank immediately following the first memory bank in the first sequential order to generate a second sequential order for the set of memory banks;

performing a set of writes to store the plurality of FIFO buffer data portions into the set of memory banks in accordance with the second sequential order.

16 . The media of claim 15 , further storing instructions that, when executed by the one or more computing devices, cause further performance of: generating a bit vector corresponding to the first sequential order along with a swap bit set to indicate that a swapping operation is performed to generate the second sequential order from the first sequential order.

17 . The media of claim 16 , further storing instructions that, when executed by the one or more computing devices, cause further performance of:

at one or more subsequent clock cycles after the current clock cycle, receiving a request for retrieving the set of FIFO buffer data portions in the FIFO buffer implemented with the plurality of memory banks;

accessing the bit vector and a swap bit to determine whether the swap bit indicates that the swapping operation has been performed to generate the second sequential order from the first sequential order, wherein the first sequential order is indicated with the bit vector;

in response to determining that the swap bit indicates that the swapping operation has been performed to generate the second sequential order from the first sequential order, perform a set of reads to retrieve the set of FIFO buffer data portions from the set of memory banks in accordance with the second sequential order.

18 . The media of claim 15 , further storing instructions that, when executed by the one or more computing devices, cause further performance of: generating a bit vector corresponding to the first sequential order along with a swapping bit set to indicate that a swapping operation is performed to generate the second sequential order from the first sequential order.

19 . The media of claim 15 , wherein each write in the set of writes stores a respective in the set of FIFO buffer data portions into a respective memory bank in the set of memory banks.

20 . The media of claim 15 , wherein a set of reads is performed in the current clock cycle to retrieve FIFO buffer data portions from a second set of memory banks in the plurality of memory banks, wherein the one or more memory bank selection methods excludes each and every memory bank in the second set of memory banks from being selected into the set of memory banks used to perform the set of writes in the current clock cycle.

21 . The media of claim 15 , further storing instructions that, when executed by the one or more computing devices, cause further performance of:

at a second current clock cycle, receiving a second request for storing a second set of FIFO buffer data portions in the FIFO buffer implemented with the plurality of memory banks;

in response to the second request for storing the second set of FIFO buffer data portions, applying the one or more memory bank selection methods to select, from among the plurality of memory banks, a second set of memory banks ordered in a third sequential order;

determining whether the second set of memory banks as ordered in the third sequential order starts with a third memory bank identical to a previous memory bank written in a previous clock cycle, wherein the previous clock cycle immediately precedes the second current clock cycle, wherein a previous sequential order used to order a previous set of memory banks selected for a previous set of writes in the previous clock cycle ends with the previous memory bank;

in response to determining that the second set of memory banks as ordered in the third sequential order starts with the third memory bank not identical to the previous memory bank written in the previous clock cycle, performing a second set of writes to store the second set of FIFO buffer data portions into the second set of memory banks in accordance with the third sequential order.