Analog correlated multi-sampling techniques
Systems, devices, and methods relating to analog-to-digital converters (ADCs) having a split digital-to-analog converters (DAC) are described. The ADC may include sample and hold circuitry having multiple sample and hold branches, with each branch coupled to a separate DAC. The total capacitor area for all of the separate DACs in the ADC may sum to the total capacitor area required in a non-branched ADC configuration. Exemplary ADCs may enable analog correlated multi-sampling to reduce noise or otherwise improve signal-to-noise ratio. The ADC may include a configurable gain factor and a configurable number of correlated multi-sampling reads. Exemplary embodiments include an image sensor having a pixel output coupled with a readout circuitry, wherein the readout circuitry includes an ADC having a split-DAC architecture, enabling lower read noise and higher framerates with lower power usage.
1 . An image sensor, comprising:
a pixel comprising an output; and
a readout circuitry coupled to the pixel output, wherein the readout circuitry comprises:
an amplifier having an input and an output, wherein the input is coupled with the pixel output; and
an analog-to-digital converter (ADC) comprising:
a sample and hold (SH) circuitry comprising an input, an output, a first SH branch coupled between the SH circuitry input and the SH circuitry output, and a second SH branch coupled in parallel with the first SH branch between the SH circuitry input and the SH circuitry output, wherein:
the SH circuitry input is coupled with the amplifier output; and
the SH circuitry output is configured to determine a combined value based on the first SH branch and second SH branch;
a first digital-to-analog converter (DAC) coupled with the first SH branch; and
a second DAC coupled with the second SH branch.
2 . The image sensor of claim 1 , wherein:
the ADC comprises a third DAC and a fourth DAC; and
the SH circuitry comprises a third SH branch and a fourth SH branch, wherein:
the first SH branch, second SH branch, third SH branch, and fourth SH branch are coupled in parallel between the SH circuitry input and the SH circuitry output;
the SH circuitry output is configured to determine the combined value based on the first SH branch, second SH branch, third SH branch, and fourth SH branch;
the third DAC is coupled with the third SH branch; and
the fourth DAC is coupled with the fourth SH branch.
3 . The image sensor of claim 1 , wherein:
the first SH branch comprises a first switch coupled, at a first node, in series with a first capacitor, wherein the first DAC is coupled with the first SH branch at the first node; and
the second SH branch comprises a second switch coupled, at a second node, in series with a second capacitor, wherein the second DAC is coupled with the second SH branch at the second node.
4 . The image sensor of claim 1 , wherein the ADC comprises:
a comparator comprising a first input, a second input, and an output, wherein:
the comparator is configured to provide a comparison result on the comparator output; and
the comparison result is based on the first input and the second input; and
an ADC control circuitry comprising an input and an output, wherein:
the ADC control circuitry input is coupled with the comparator output; and
the ADC control circuitry is configured to control the first DAC and the second DAC via the ADC control circuitry output.
5 . The image sensor of claim 4 , wherein:
the comparator second input is coupled with a reference signal;
the comparator is configured to compare the reference signal to the combined value; and
the ADC control circuitry is configured to control the first DAC and the second DAC according to a successive approximation (SA) algorithm.
6 . The image sensor of claim 5 , wherein:
the first DAC comprises a first plurality of switched capacitors;
the second DAC comprises a second plurality of switched capacitors;
the ADC control circuitry is configured to switch the first plurality of switched capacitors and switch the second plurality of switched capacitors according to the SA algorithm; and
the ADC is configured to provide a digital representation of the SH circuitry input based on one or more comparison results provided by the comparator.
7 . The image sensor of claim 1 , wherein the image sensor is configured to:
control the first SH branch to store, at a first time, a first reset value;
control the second SH branch to store, at a second time, a second reset value;
perform, using the ADC, a first analog-to-digital (AD) conversion of a first combined value to generate a digital reset value, wherein the first combined value is based on the first and second reset values;
control the first SH branch to store, at a third time, a first image value;
control the second SH branch to store, at a fourth time, a second image value;
perform, using the ADC, a second AD conversion of a second combined value to generate a digital image value, wherein the second combined value is based on the first and second image values; and
determine a final pixel value based on the digital image value and the digital reset value.
8 . The image sensor of claim 7 , wherein:
the second time is a time period T CMS after the first time, wherein the time period T CMS corresponds to a minimum time required to provide an uncorrelation of noise; and
the fourth time is the time period T CMS after the third time.
9 . A method for performing a readout of an image sensor pixel using an analog-to-digital converter (ADC), comprising:
storing, at a first time and using a first sample and hold (SH) branch of an SH circuitry, a first reset value based on a first output of the pixel;
storing, at a second time and using a second SH branch of the SH circuitry, a second reset value based on the first output, wherein:
the first SH branch is coupled in parallel with the second SH branch between an input of the SH circuitry and an output of the SH circuitry; and
the SH circuitry output provides a combined value based on the first SH branch and the second SH branch;
performing, using the ADC, a first analog-to-digital (AD) conversion of a first combined value from the SH circuitry output to generate a digital reset value;
storing, at a third time and using the first SH branch, a first image value based on a second output of the pixel;
storing, at a fourth time and using the second SH branch, a second image value based on the second output;
performing, using the ADC, a second AD conversion of a second combined value from the SH circuitry output to generate a digital image value; and
determining a final pixel value based on the digital reset value and the digital image value.
10 . The method of claim 9 , further comprising:
storing, at a fifth time and using a third SH branch of the SH circuitry, a third reset value based on the first output;
storing, at a sixth time and using a fourth SH branch of the SH circuitry, a fourth reset value based on the first output;
storing, at a seventh time and using the third SH branch, a third image value based on the second output;
storing, at an eight time and using the fourth SH branch, a fourth image value based on the first output, wherein:
the first, second, third, and fourth SH branches are coupled in parallel between the input of the SH circuitry and the output of the SH circuitry; and
the SH circuitry output provides the combined value based on the first SH branch, second SH branch, third SH branch, and fourth SH branch.
11 . The method of claim 9 , wherein the ADC comprises a first digital-to-analog converter (DAC) coupled with the first SH branch and a second DAC coupled with the second SH branch, and wherein:
performing the first AD conversion comprises concurrently controlling the first DAC and the second DAC; and
performing the second AD conversion comprises concurrently controlling the first DAC and the second DAC.
12 . The method of claim 11 , wherein performing each AD conversion comprises performing, by the ADC, a successive approximation (SA) algorithm.
13 . The method of claim 12 , wherein:
the first DAC comprises a first array of switched capacitors;
the second DAC comprises a second array of switched capacitors;
controlling the first DAC comprises switching the first array of switched capacitors according to the SA algorithm; and
controlling the second DAC comprises switching the second array of switched capacitors according to the SA algorithm.
14 . The method of claim 9 , wherein determining the final pixel value comprises subtracting the digital reset value from the digital image value.
15 . The method of claim 9 , wherein the second time is a time period T CMS after the first time, wherein the time period T CMS corresponds to a minimum time required to provide an uncorrelation of noise.
16 . The method of claim 15 , wherein the fourth time is the time period T CMS after the third time.
17 . An analog-to-digital converter (ADC), comprising:
a sample and hold (SH) circuitry comprising an input, an output, a first SH branch coupled between the SH circuitry input and the SH circuitry output, and a second SH branch coupled in parallel with the first SH branch between the SH circuitry input and the SH circuitry output, wherein:
the SH circuitry input is coupled with an input of the ADC; and
the SH circuitry output is configured to determine a combined value based on the first SH branch and second SH branch;
a first digital-to-analog converter (DAC) coupled with a sample hold node of the first SH branch; and
a second DAC coupled with a sample hold node of the second SH branch.
18 . The ADC of claim 17 , further comprising:
a comparator comprising a first input, a second input, and an output, wherein:
the comparator is configured to provide, on the comparator output, a comparison result based on the first and second comparator inputs; and
an ADC control circuitry comprising an input and an output, wherein:
the ADC control circuitry input is coupled with the comparator output; and
the ADC control circuitry is configured to control the first DAC and the second DAC via the ADC control circuitry output.
19 . The ADC of claim 18 , wherein the ADC control circuitry is configured to control the first DAC and the second DAC according to a successive approximation (SA) algorithm.
20 . The ADC of claim 19 , wherein:
the first DAC comprises a first plurality of switched capacitors;
the second DAC comprises a second plurality of switched capacitors;
the ADC control circuitry is configured to switch the first plurality of switched capacitors and switch the second plurality of switched capacitors according to the SA algorithm; and
the ADC is configured to provide a digital representation of the SH circuitry input based on one or more comparison results provided by the comparator.