Column signal processing unit and solid-state imaging device

1 . A column signal processing unit, comprising:

a current control circuit electrically connected between a data signal line and a supply reference potential; and

a feedback circuit configured to reduce a capacitive load of the data signal line,

wherein a feedback path of the feedback circuit comprises a series connection of (i) a feedback capacitor including two conductive materials separated by a non-conductive material and (ii) a delay element, and

wherein the delay element is configured to increase a time delay in the feedback path.

2 . The column signal processing unit according to claim 1 ,

wherein the feedback circuit comprises a first switch, and

wherein the delay element and the first switch are electrically connected in parallel.

3 . The column signal processing unit according to claim 1 , wherein the delay element comprises a load path of a first transistor.

4 . The column signal processing unit according to claim 3 , further comprising:

a transistor bias circuit configured to supply a first bias voltage to a gate of the first transistor.

5 . The column signal processing unit according to claim 4 ,

wherein the transistor bias circuit comprises a bias voltage capacitor and a second switch,

wherein the bias voltage capacitor is connected to the gate of the first transistor, and

wherein the second switch is configured to connect the bias voltage capacitor with a bias voltage source in an on-state.

6 . The column signal processing unit according to claim 5 ,

wherein the feedback path comprises a first switch electrically connected in parallel with the delay element, and

wherein the first switch and the second switch are controllable through a first control signal.

7 . The column signal processing unit according to claim 1 ,

wherein the feedback circuit comprises an amplifier circuit,

wherein an input of the amplifier circuit is connected to the data signal line, and

wherein an output of the amplifier circuit is connected to a second side of the feedback path.

8 . The column signal processing unit according to claim 7 ,

wherein the amplifier circuit comprises a second transistor and a third transistor,

wherein load paths of the second transistor and the third transistor are electrically connected in series, and

wherein the input of the amplifier circuit is connected to a gate of the second transistor.

9 . The column signal processing unit according to claim 1 ,

wherein the feedback circuit further comprises a sense element connected in series between the data signal line and the current control circuit, and

wherein a first side of the feedback path is connected to a first node between the sense element and the current control circuit.

10 . The column signal processing unit according to claim 9 , wherein the sense element comprises a fourth transistor and the current control circuit comprises a fifth transistor.

11 . The column signal processing unit according to claim 10 ,

wherein the fifth transistor and the fourth transistor have a same gate width.

12 . The column signal processing unit according to claim 1 , further comprising a bias circuit configured to supply a first bias voltage to the delay element.

13 . A solid-state imaging device, comprising:

a plurality of pixel circuits,

wherein each pixel circuit is configured to generate a pixel output signal with an amplitude related to an intensity of detected light, and

wherein the pixel circuits are connected to a data signal line; and

a column signal processing unit, wherein the column signal processing unit comprises:

a current control circuit electrically connected between the data signal line and a supply reference potential, and

a feedback circuit configured to reduce a capacitive load of the data signal line,

wherein a feedback path of the feedback circuit comprises (i) a feedback capacitor including two conductive materials separated by a non-conductive material and (ii) a delay element electrically connected in series, and

wherein the delay element is configured to increase a time delay in the feedback path.

14 . The solid-state imaging device according to claim 13 , further comprising a sensor controller,

wherein the feedback circuit comprises a first switch,

wherein the delay element and the first switch are electrically connected in parallel, and

wherein the sensor controller is configured to generate and output a first control signal for the first switch.

15 . The solid-state imaging device according to claim 14 , wherein the sensor controller is configured to generate and output the first control signal in response to a synchronization signal.

16 . The solid-state imaging device according to claim 14 , wherein the column signal processing unit is configured to use a synchronization signal as the first control signal.