Structurally enhanced filtering of circuit board planes
Techniques and assemblies for enhanced circuit board layouts and circuit configurations are presented. In one example, an apparatus includes a circuit board having a power plane configured to carry electrical current from a power supply circuit to load circuitry. The power plane comprises a fence region that establishes an increased characteristic impedance of the power plane and has vias arrayed across the power plane which perforate the power plane and electrically couple to a ground plane of the circuit board. A filter is established at the fence region by at least capacitance elements electrically coupled between the power plane and the ground plane, the filter configured to route at least a portion of noise carried by the power plane to the ground plane at the fence region.
1 . An apparatus, comprising:
a circuit board having a power plane configured to carry electrical current from a power supply circuit to load circuitry;
the power plane comprising a fence region comprising a neckdown of a conductive area having reduced planar width with respect to an adjacent region of the power plane supplying the load circuitry, wherein the fence region is configured to pass DC current carried by the power plane and establish an increased characteristic impedance of the power plane at the fence region with respect to noise having a frequency range using at least a set of vias arrayed across the fence region of the power plane which perforate the power plane and restrict the conductive area of the power plane; and
a filter established at the fence region by at least capacitance elements electrically coupled between a ground plane and additional vias to the power plane, the filter configured to shunt at least a portion of the noise affected by the increased characteristic impedance to the ground plane at the fence region.
2 . The apparatus of claim 1 , wherein the capacitance elements comprise capacitors having a selected quantity of different capacitance values interspersed among the array, each of the different capacitance values selected to route a selected frequency portion of the frequency range of the noise to the ground plane from the power plane.
3 . The apparatus of claim 1 , wherein first terminals of the array of capacitors couple to the power plane over corresponding ones of the additional vias that penetrate through at least the ground plane; and
wherein second terminals of the array of the capacitors couple to the ground plane.
4 . The apparatus of claim 3 , wherein the ground plane is formed on a surface layer of the circuit board, and the power plane is formed on an internal layer of the circuit board.
5 . The apparatus of claim 1 , wherein the ground plane is formed on a first external surface of the circuit board and is coupled to a second ground plane by the vias arrayed across the fence region; and
wherein the power plane is formed on an internal layer of the circuit board positioned between the ground plane and the second ground plane.
6 . The apparatus of claim 5 , wherein the filter is further established by additional capacitance elements arrayed across the fence region on a second external surface of the circuit board and electrically coupled between the second ground plane and the power plane.
7 . The apparatus of claim 1 , comprising:
board-level shield footprints configured to couple to a board-level shield component that shields against at least a portion of radiated emissions generated by the load circuitry;
wherein the fence region is positioned proximate to the board-level shield footprints; and
wherein the filter is configured to shield against at least a portion of conducted emissions generated by the load circuitry.
8 . The apparatus of claim 1 , wherein the fence region is formed to establish an increased characteristic impedance for an additional power plane; and comprising:
additional capacitance elements electrically coupled between the additional power plane and the ground plane at the fence region, the additional capacitance elements configured to route at least a portion of noise carried by the additional power plane to the ground plane at the fence region.
9 . A method, comprising:
forming a circuit board having a power plane that establishes a pathway for electrical current from power supply circuitry to load circuitry;
forming the power plane as having a fence region comprising a neckdown of a conductive area having reduced planar width with respect to an adjacent region of the power plane supplying the load circuitry, wherein the fence region is configured to pass DC current carried by the power plane and establish an increased characteristic impedance of the power plane at the fence region with respect to noise having a frequency range with at least a set of vias arrayed across the fence region of the power plane which perforate the power plane and restrict a conductive area of the power plane;
forming footprints for surface mount capacitors arrayed across the fence region; and
forming additional vias in the circuit board coupling terminals of the surface mount capacitors to the power plane.
10 . The method of claim 9 , comprising:
populating the surface mount capacitors onto the footprints to form a filter configured to shunt at least a portion of the noise carried by the power plane and affected by the increased characteristic impedance to a ground plane at the fence region.
11 . The method of claim 10 , wherein the surface mount capacitors comprise a selected quantity of different capacitance values interspersed among each other, with each of the different capacitance values selected to route a selected frequency portion of the frequency range of the noise to the ground plane from the power plane.
12 . The method of claim 9 , wherein second terminals of the array of capacitors couple to a ground plane at the fence region.
13 . The method of claim 9 , wherein a ground plane is formed on a surface layer of the circuit board, and the power plane is formed on an internal layer of the circuit board.
14 . The method of claim 9 , wherein a ground plane is formed on a first external surface of the circuit board and is coupled to a second ground plane by the vias arrayed across the fence region; and
wherein the power plane is formed on an internal layer of the circuit board positioned between the ground plane and the second ground plane.
15 . The method of claim 9 , comprising:
forming board-level shield footprints on the circuit board proximate to the fence region that are configured to couple to a board-level shield component.
16 . An assembly, comprising:
a circuit board comprising:
a ground plane formed on a first surface of the circuit board;
a power plane formed on an internal layer of the circuit board and configured to provide a pathway for electrical current from power supply circuitry to load circuitry, wherein the power plane comprises a fence region comprising a neckdown of a conductive area having reduced planar width with respect to an adjacent region of the power plane supplying the load circuitry, wherein the fence region is configured to pass DC current carried by the power plane and establish an increased characteristic impedance of the power plane at the fence region with respect to noise having a frequency range with at least a set of vias arrayed across the fence region of the power plane which perforate the power plane and restrict a conductive area of the power plane; and
footprints for surface mount capacitors arrayed across the fence region, with first terminals of the footprints coupled through additional vias to the power plane and second terminals of the footprints coupled to the ground plane.
17 . The assembly of claim 16 , comprising:
capacitors populated onto the footprints that form a filter configured to shunt at least a portion of the noise carried by the power plane and affected by the increased characteristic impedance to the ground plane at the fence region.
18 . The assembly of claim 17 , wherein the capacitors comprise a selected quantity of different capacitance values interspersed among each other, with each of the different capacitance values selected to route a selected frequency portion of the frequency range of the noise to the ground plane from the power plane.
19 . The assembly of claim 16 , the circuit board comprising:
board-level shield footprints arrayed across the fence region and coupled to the ground plane, wherein the board-level shield footprints are configured to couple to a board-level shield component.